Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model

Wang Feng; Xie Yuan

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Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model

机译：使用精确电屏蔽模型的组合逻辑软错误率分析

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Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these models, we propose and validate the transient pulse generation model and propagation model for soft error rate analysis. The pulse generated by our pulse generation model matches well with that of HSPICE simulation, and the pulse propagation model provides nearly one order of magnitude improvement in accuracy over the previous models. Using these two models, we propose an accurate and efficient block-based soft error rate analysis method for combinational logic circuits.

机译：准确的电掩蔽建模在组合逻辑电路的软错误率分析中提出了重大挑战。在本文中，我们使用查表MOSFET模型来准确捕获亚微米MOS晶体管的非线性特性。基于这些模型，我们提出并验证了用于软错误率分析的瞬态脉冲生成模型和传播模型。我们的脉冲生成模型生成的脉冲与HSPICE仿真的脉冲匹配得很好，并且脉冲传播模型的准确性比以前的模型提高了近一个数量级。利用这两个模型，我们为组合逻辑电路提出了一种准确，高效的基于块的软错误率分析方法。

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《Dependable and Secure Computing, IEEE Transactions on》 |2011年第1期|p.137-146|共10页
作者
Wang Feng; Xie Yuan;
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作者单位

Pennsylvania State University, University Park;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Reliability; combinational logic.; fault injection; simulation;

机译：可靠性;组合逻辑;故障注入;仿真;

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1. Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling [J] . Nazarian S., Fatemi H., Pedram M. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2011,第1期

机译：使用电流源建模的组合逻辑和顺序逻辑单元的准确时序和噪声分析
2. Exploiting component dependency for accurate and efficient soft error analysis via Probabilistic Graphical Models [J] . Jiajia Jiao, Da-Cheng Juan, Diana Marculescu, Microelectronics & Reliability . 2015,第1期

机译：利用组件依赖性通过概率图形模型进行准确，高效的软错误分析
3. Soft error generation analysis in combinational logic circuits [J] . Ding Qian, Wang Yu, Luo Rong, Journal of Semiconductors . 2010,第9期

机译：组合逻辑电路中的软错误生成分析
4. Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model [C] . Feng Wang, Yuan Xie, R. Rajaraman, International Conference on VLSI Design . 2007

机译：组合逻辑使用精确电屏蔽模型的软错误率分析
5. Soft errors in logic circuits: Analysis and modeling. [D] . Ramanarayanan, Rajaraman. 2007

机译：逻辑电路中的软错误：分析和建模。
6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
7. Soft error rate analysis for combinational logic using an accurate electrical masking model [O] . Feng Wang, Yuan Xie, R. Rajaraman, 2014

机译：使用精确电屏蔽模型的组合逻辑的软错误率分析
8. Foundation for the Accurate Prediction of the Soft Error Vulnerability of Scientific Applications [R] . Bronevetsky, G., de Supinski, B., Schulz, M. 2009

机译：准确预测科学应用软错误脆弱性的基础

Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model

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