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首页> 外文期刊>IEEE transactions on dependable and secure computing >Design and Implementation of the Ascend Secure Processor
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Design and Implementation of the Ascend Secure Processor

机译：上升安全处理器的设计与实现

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This paper presents post-silicon results for the Ascend secure processor, taped out in a 32 nm SOI process. Ascend prevents information leakage over a processor's digital I/O pins-in particular, the processor's requests to external memory-and certifies the program's execution by verifying the integrity of the external memory. In secure processor design, encrypting main memory is not sufficient for security because where and when memory is accessed reveals secret information. To this end, Ascend is equipped with a hardware Oblivious RAM (ORAM) controller, which obfuscates the address bus by reshuffling memory as it is accessed. To our knowledge, Ascend is the first prototyping of ORAM in custom silicon. Ascend has also been carefully engineered to ensure its timing behaviors are independent of user private data. In 32 nm silicon, all security components combined (the ORAM controller, which includes 12 AES rounds and one SHA-3 hash unit) impose a moderate area overhead of 0.51 mm(2). Post tape-out, the security components of the Ascend chip have been successfully tested at 857 MHz and 1.1 V, at which point they consume 299 mW of power.
机译：本文介绍了Ascend Cref处理器的硅后果结果，在32 nm SOI过程中占用。 Ascend防止信息泄漏在处理器的数字I / O引脚上 - 特别是处理器对外部内存的请求 - 并通过验证外部存储器的完整性来证明程序的执行。在安全的处理器设计中，加密主存储器不足以用于安全性，因为访问内存时以及当存储器时显示秘密信息。为此，Ascend配备了硬件忽略的RAM（ORAM）控制器，其在访问时通过重新洗脱存储器来抵消地址总线。为了我们的知识，Ascend是奥地姆在定制硅中的第一个原型。也经过精心设计，以确保其时序行为独立于用户私有数据。在32nm硅中，所有安全部件组合（包括12个A形圆形和一个SHA-3散列单元的ORAM控制器）施加0.51mm（2）的中等面积开销。胶带后，上升芯片的安全组件已在857 MHz和1.1 V成功测试，此时它们消耗299兆瓦的功率。

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