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首页> 外文期刊>IEEE transactions on electronics packaging manufacturing >A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification
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A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification

机译：面积阵列焊料互连封装组装过程的理论良率模型，并进行了实验验证

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摘要

This paper presents a theoretical yield model for area array solder interconnect process. To achieve a successful solder joint, contact between the solder ball and its associated wettable pad area is essential because without contact, the solder ball cannot initiate wetting its associated pad and, finally, is found an open defect. When an area array solder joints are made simultaneously, it may happen that some of the solder joints in a chip cannot make contact with their associated pads because of the variations of design parameters such as solder ball size, pad size and height, substrate warpage, etc. The yield model provides the relationships of the interconnect yield to the statistical variations of the design parameters. A series of experiments were performed with specially designed area array flip-chips and substrates to verify the model, focusing on the effects of the solder ball size variation and the number of solder joints on interconnect yield. The experimental observations agree well with the model prediction.
机译：本文提出了一种用于区域阵列焊料互连工艺的理论良率模型。为了实现成功的焊点，焊球及其相关的可湿性焊盘区域之间的接触是必不可少的，因为如果没有接触，焊球将无法开始润湿其相关的焊盘并最终发现一个开放的缺陷。同时制作区域阵列焊点时，由于设计参数（例如焊球尺寸，焊垫大小和高度，基板翘曲，良率模型提供了互连良率与设计参数的统计变化之间的关系。使用专门设计的面积阵列倒装芯片和基板进行了一系列实验，以验证模型，重点是焊球尺寸变化和焊点数量对互连良率的影响。实验观察与模型预测吻合良好。

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