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Energy Consumption of VLSI Decoders

机译:VLSI解码器的能耗

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Thompson’s model of very large scale integration computation relates the energy of a computation to the product of the circuit area and the number of clock cycles needed to carry out the computation. It is shown that for any sequence of increasing block-length decoder circuits implemented according to this model, if the probability of block error is asymptotically less than 1/2 then the energy of the computation scales at least as , and so the energy of decoding per bit must scale at least as . This implies that the average energy per decoded bit must approach infinity for any sequence of decoders that approaches capacity. The analysis techniques used are then extended to show that for any sequence of increasing block-length serial decoders, if the asymptotic block error probability is less than 1/2 then the energy scales at least as fast as . In a very general case that allows for the number of output pins to vary with block length, it is shown that the energy must scale as . A simple example is provided of a class of circuits performing low-density parity-check decoding whose energy complexity scales as .
机译:汤普森的大规模集成计算模型将计算的能量与电路面积和执行计算所需的时钟周期数的乘积相关联。结果表明,对于根据该模型实现的任何增加块长的解码器电路序列,如果块错误的概率渐近小于1/2,则计算能量至少应为,因此解码能量每位必须至少缩放为。这意味着对于接近容量的任何解码器序列,每个解码位的平均能量必须接近无穷大。然后扩展所使用的分析技术,以表明对于块长度递增的串行解码器的任何序列,如果渐近块错误概率小于1/2,则能量的缩放速度至少与一样快。在非常普遍的情况下,允许输出引脚的数量随模块长度而变化,这表明能量必须按比例缩放。提供了一个简单的例子,说明了一类执行低密度奇偶校验解码的电路,其能量复杂度为。

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