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首页> 外文期刊>IEEE Transactions on Information Theory >Algorithm and architecture for a Galois field multiplicative arithmetic processor
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Algorithm and architecture for a Galois field multiplicative arithmetic processor

机译：Galois现场乘法算术处理器的算法和体系结构

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摘要

We present a new algorithm for generic multiplicative computations of the form ab/c in GF(p/sup m/), including multiplication, inversion, squaring, and division. The algorithm is based on solving a sequence of congruences that are derived from the theory of Grobner bases in modules over the polynomial ring GF(p)[x]. Its corresponding hardware and software architectures can be successfully used in applications such as error control coding and cryptography. We describe a versatile circuit associated with the algorithm for the most important case p=2. The same hardware can be used for a range of field sizes thus permitting applications in which different levels of error control or of security are required by different classes of user. The operations listed are all performed by the hardware in the same number of clock cycles, which prevents certain side-channel attacks. The loss in performance by having 2m iterations for multiplication is compensated by the full parameterization of the Galois field and the ability to perform division and multiplication in parallel.
机译：我们提出了一种用于GF（p / sup m /）中ab / c形式的通用乘法计算的新算法，包括乘法，求逆，平方和除法。该算法基于求解从多项式环GF（p）[x]上的模块中的Grobner基理论导出的同余序列。其相应的硬件和软件体系结构可以成功地用于错误控制编码和加密等应用程序中。我们描述了与最重要的情况p = 2的算法相关的通用电路。相同的硬件可用于各种字段大小，因此允许不同类别的用户需要不同级别的错误控制或安全性的应用。列出的所有操作均由硬件在相同数量的时钟周期内执行，从而防止了某些边信道攻击。 Galois字段的完整参数化以及并行执行除法和乘法的能力可以弥补因进行2m次乘法运算而造成的性能损失。

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