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首页> 外文期刊>IEEE Transactions on Magnetics >Parallelism in analog and digital PRML magnetic disk read channel equalizers
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Parallelism in analog and digital PRML magnetic disk read channel equalizers

机译：模拟和数字PRML磁盘读取通道均衡器中的并行性

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摘要

Analog pre-equalization can play an important role in the performance and monolithic implementation of high speed PRML read channels employing detection in the digital domain by reducing the number of quantization levels required in the analog-to-digital converter. The use of the 3-tap raised cosine equalizer as an analog pre-equalizer in a read channel employing digital adaptive equalization is examined. Following this, a parallel filter architecture suitable for implementation of high speed finite-impulse response filters (including the cosine equalizer) in both the analog and digital domain is described. This parallel filter architecture has been used in the analog domain in both a decimation filter and cosine equalizer in a prototype analog-to-digital interface and in the digital domain in a prototype digital adaptive equalizer/Viterbi sequence detector. Both circuits were fabricated in conservative 1.2 /spl mu/m CMOS technologies and operate with output sampling rates of 100 MHz.
机译：通过减少模数转换器所需的量化级别数量，模拟预均衡功能在高速PRML读取通道的性能和整体实现中起着重要作用，该通道在数字域中采用检测功能。在使用数字自适应均衡的读取通道中，研究了3抽头升高余弦均衡器作为模拟预均衡器的使用。随后，描述了适用于在模拟和数字域中实现高速有限冲激响应滤波器（包括余弦均衡器）的并行滤波器架构。这种并行滤波器架构已在原型模数接口的抽取滤波器和余弦均衡器的模拟域以及原型数字自适应均衡器/维特比序列检测器的数字域的模拟域中使用。两种电路均采用保守的1.2 / spl mu / m CMOS技术制造，并以100 MHz的输出采样速率工作。

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