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机译:用于混合CMOS / MTJ逻辑电路的可靠性增强的分离式预充电感应放大器
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Center de Nanoscience et de Nanotechnologies (C2N-Orsay), University of Paris-Sud, Orsay, France;
Fert Beijing Institute, BDBC, Beihang University, Beijing, China;
Sensors; Discharges (electric); Magnetic tunneling; Logic circuits; Integrated circuit reliability; Resistance;
机译:用于深亚微米MTJ / CMOS混合逻辑电路的分离式预充电感应放大器
机译:适用于MTJ / CMOS混合逻辑电路的高速,高稳定性和低功耗传感放大器
机译:增强可靠性的混合CMOS / MTJ逻辑电路架构
机译:增强可靠性的混合CMOS / MTJ逻辑电路
机译:晶体管放置算法,用于CMOS / BiCMOS逻辑和接口电路的自动布局合成。
机译:基于光纤的单壁碳纳米管晶体管电路对类似CMOS电路的稳定逻辑操作
机译:从MTJ设备到混合CMOS / MTJ电路:综述