Negative Capacitance for Boosting Tunnel FET performance

Masaharu Kobayashi; Kyungmin Jang; Nozomu Ueyama; Toshiro Hiramoto

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Negative Capacitance for Boosting Tunnel FET performance

机译：负电容可提升隧道FET性能

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We have proposed and investigated a super steep subthreshold slope transistor by introducing negative capacitance of a ferroelectric HfO2 gate insulator to a vertical tunnel FET for energy efficient computing. The channel structure and gate insulator are systematically designed to maximize the Ion/Ioff ratio. The simulation study reveals that the electric field at the tunnel junction can be effectively enhanced by potential amplification due to the negative capacitance. The enhanced electric field increases the band-to-band tunneling rate and Ion/Ioff ratio, which results in 10× higher energy efficiency than in tunnel FET.

机译：我们通过将铁电HfO2栅极绝缘体的负电容引入垂直隧道FET来进行能效计算，从而提出并研究了一种超陡峭的亚阈值斜率晶体管。沟道结构和栅极绝缘体经过系统设计，可最大程度地提高Ion / Ioff比。仿真研究表明，由于负电容，电势放大可以有效地增强隧道结处的电场。增强的电场提高了带间隧穿速率和Ion / Ioff比，这导致其能量效率比隧道FET高10倍。

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来源
《IEEE transactions on nanotechnology》 |2017年第2期|253-258|共6页
作者
Masaharu Kobayashi; Kyungmin Jang; Nozomu Ueyama; Toshiro Hiramoto;
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作者单位

Institute of Industrial Science, University of Tokyo, Tokyo, Japan;

Institute of Industrial Science, University of Tokyo, Tokyo, Japan;

Institute of Industrial Science, University of Tokyo, Tokyo, Japan;

Institute of Industrial Science, University of Tokyo, Tokyo, Japan;

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原文格式 PDF
正文语种 eng
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关键词
Logic gates; TFETs; Insulators; Tunneling; Capacitance; Electric fields;

机译：逻辑门;TFET;绝缘子;隧道;电容;电场;

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1. Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study [J] . Ali Saeidi, Farzan Jazaeri, Francesco Bellando, IEEE Electron Device Letters . 2017,第10期

机译：负电容作为隧道FET和MOSFET的性能提升器：一项实验研究
2. Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances [J] . Liang Yuhua, Zhu Zhangming, Li Xueqing, IEEE transactions on very large scale integration (VLSI) systems . 2019,第12期

机译：利用负电容FET提高模拟电路性能
3. Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance [J] . Saeidi Ali, Jazaeri Farzan, Stolichnov Igor, Nanotechnology . 2018,第9期

机译：滞回和非滞回负电容对隧道FETS直流性能的影响
4. Negative Capacitance Tunnel FETs: Experimental Demonstration of Outstanding Simultaneous Boosting of On-current, Transconductance, Overdrive, and Swing [C] . A. Saeidi, F. Jazaeri, I. Stolichnov, IEEE Silicon Nanoelectronics Workshop . 2017

机译：负电容隧道FET：实验演示优异的同时提高电流，跨导，过驱动和摆动
5. Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs [D] . Sharma, Ankit. 2018

机译：用于低功率计算的低于10nm晶体管：隧道FET和负电容FET
6. Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors [O] . Ali Saeidi, Farzan Jazaeri, Igor Stolichnov, -1

机译：负电容作为互补MOS晶体管的通用数字和模拟性能增强器
7. Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study [O] . Ali Saeidi, Farzan Jazaeri, Francesco Bellando, 2017

机译：负电容作为隧道FET和MOSFET的性能助推器：实验研究

Negative Capacitance for Boosting Tunnel FET performance

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