...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE transactions on nanotechnology >Benchmarking nanotechnology for high-performance and low-power logic transistor applications
【24h】

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

机译：高性能和低功耗逻辑晶体管应用的基准纳米技术

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.
机译：最近，在用于未来纳米电子应用的新型纳米技术的研究中取得了巨大进展。尤其是，一些新兴的纳米电子器件，例如碳纳米管场效应晶体管（FET），Si纳米线FET和平面III-V化合物半导体（例如InSb，InAs）FET，都有望成为潜在的集成候选器件到硅平台上，以增强电路功能并扩展摩尔定律。对于高性能和低功耗逻辑晶体管应用，重要的是，经常将这些研究设备与现有的Si逻辑晶体管数据进行基准比较，以评估研究的进展。在本文中，我们使用四个关键的器件指标来将这些新兴的纳米电子器件与最新的平面和非平面Si逻辑晶体管进行比较。这四个指标包括：1）CV / I或固有栅极延迟与物理栅极长度L / sub g /的关系； 2）能量延迟乘积与L / sub g /的关系； 3）亚阈值斜率对L / sub g /; 4）CV / I与开/关状态电流比I / sub ON // I / sub OFF /。基准测试的结果表明，尽管这些新颖的纳米电子器件显示了未来逻辑应用的希望和机遇，但在器件特性和静电方面仍存在需要克服的缺点。我们相信基准测试是加速逻辑晶体管应用纳米技术研究进展的关键因素。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号