Nonphotolithographic nanoscale memory density prospects

DeHon A.; Goldstein S.C.; Kuekes P.J.; Lincoln P.

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Nonphotolithographic nanoscale memory density prospects

机译：非光刻纳米级存储密度前景

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Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations.

机译：现在出现了使用自下而上的自组装构造分子级电子线路和开关的技术。这就开辟了构建纳米级电路和存储器的可能性，其中有源器件只有几纳米平方，导线间距可能在十纳米的数量级。可以在不使用光刻的情况下按此比例定义特征。与常规的光刻集成电路相比，可用的组装技术具有相对较高的缺陷率，并且只能产生非常规则的结构。但是，通过适当的内存组织，可以合理地期望这些技术提供超过10 / sup 11 / b / cm / sup 2 /的内存密度，并且对于随机读取操作，其有功功率要求低于0.6 W / Tb / s。

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《IEEE transactions on nanotechnology》 |2005年第2期|p.215-228|共14页
作者
DeHon A.; Goldstein S.C.; Kuekes P.J.; Lincoln P.;
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正文语种 eng
中图分类特种结构材料;
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molecular electronics; nanoelectronics; nanolithography; nanowires; self-assembly; storage management; switches; high defect rate; memory densities; memory organization; molecular scale electronic wires; nanoscale circuits; nonphotolithographic nanoscale memory dens;

机译：分子电子学;纳米电子学;纳米光刻;纳米线;自组装;存储管理;开关;高缺陷率;存储密度;存储组织;分子尺度的电线;纳米尺度的电路;非光刻纳米尺度的存储密度;

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Nonphotolithographic nanoscale memory density prospects

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