• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE Transactions on Nuclear Science >Single-Event Upset Tolerance Study of a Low-Voltage 13T Radiation-Hardened SRAM Bitcell
【24h】

Single-Event Upset Tolerance Study of a Low-Voltage 13T Radiation-Hardened SRAM Bitcell

机译：低电压13T抗辐射SRAM位单元的单粒子翻转耐受性研究

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

The 13T static random-access memory (SRAM) cell was designed as a low-voltage single-event upset (SEU)-tolerant device for ultralow power space applications, showing full read and write functionality down to the subthreshold voltage of 300 mV. In order to assess the SEU hardness of the device experimentally, it was tested under heavy-ion beams at the Cyclotron Resource Center, Louvain-la-Neuve, Belgium. After irradiation, bit upsets from “1” to “0” were observed, whereas bit upsets from “0” to “1” were extremely rare. Since multiple upsets occurred within addresses, we assume that in addition to random ion hits on the memory cells, the reason for the high SEU rate is ions impinging on the nonhardened peripheral circuitry. Furthermore, heavy-ion experiments and Monte Carlo simulations were performed in order to clarify the upset mechanism.
机译：13T静态随机存取存储器（SRAM）单元被设计为用于超级电源空间应用的低压单事件镦粗（SEU） - 托式设备，显示完全读取和写入功能，下降到300mV的亚阈值电压。为了通过实验评估设备的SEU硬度，在比利时Louvain-La-Neuve的重脚束下测试它在重离子束下进行测试。在照射后，观察到“1”到“0”的比特扰乱，而“0”到“1”的比特扰动非常罕见。由于在地址内发生了多个upset，我们假设除了存储器单元上的随机离子命中之外，高SEU速率的原因是冲击非硬化外围电路的离子。此外，进行重离子实验和蒙特卡罗模拟，以澄清镦粗机制。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号