Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

Maj P.; Grybos P.; Szczygiel R.; Kmon P.; Kleczek R.; Drozd A.; Otfinowski P.; Deptuch G.

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Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

机译：用于混合像素检测器的40nm CMOS工艺中原型读取芯片的匹配和噪声性能测量

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摘要

The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of pixels with the pixel size of . The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is (for the peaking time of 48 ns), the gain is , while the effective threshold dispersion is .

机译：本文提出了一种原型集成电路，该集成电路采用40 nm CMOS工艺构建，用于读出混合像素检测器。 IC的核心构成像素矩阵，像素大小为。本文介绍了IC的功能和体系结构，该IC被设计为在标准的单光子计数模式和像素间通信的单光子计数模式下工作，以减轻电荷共享的负面影响。本文重点介绍在标准单光子计数模式下运行的IC的测量结果。测得的ENC为（对于48ns的峰值时间），增益为，而有效阈值色散为。

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来源
《Nuclear Science, IEEE Transactions on》 |2015年第1期|359-367|共9页
作者
Maj P.; Grybos P.; Szczygiel R.; Kmon P.; Kleczek R.; Drozd A.; Otfinowski P.; Deptuch G.;
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作者单位

Department of Measurements and Electronics, AGH University of Science and Technology, Cracow, Poland;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Capacitance; Detectors; Integrated circuits; Noise; Photonics; Resistance; Transistors; Analog circuits; matching; noise; x-ray detectors;

机译：电容;检测器;集成电路;噪声;光子学;电阻;晶体管;模拟电路;匹配;噪声;x射线探测器;

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专利

1. FPDR90—A Low Noise, Fast Pixel Readout Chip in 90 nm CMOS Technology [J] . Szczygiel R., Grybos P., Maj P. Nuclear Science, IEEE Transactions on . 2011,第3期

机译：FPDR90 —采用90 nm CMOS技术的低噪声，快速像素读出芯片
2. Performance of hybrid photon detector prototypes with encapsulated silicon pixel detector and readout for the RICH counters of LHCb [J] . M. Campbell, K.A. George, M. Girone, Nuclear Instruments & Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment . 2003,第1a3期

机译：具有封装的硅像素探测器的混合光子探测器原型的性能以及LHCb RICH计数器的读数
3. Epitaxial hybrid pixel with triggerless readout in 130 nm Cmos technology for the Micro Vertex Detector of the Panda experiment [J] . D. CALVO, P. DE REMIGIS, G. GIRAUDO, Il Nuovo Cimento della Societa Italiana di Fisica, C. Geophysics and space physics . 2011,第6期

机译：具有130 nm Cmos技术的无触发读数的外延混合像素，用于熊猫实验的微型顶点检测器
4. First Measurements of a Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for Extreme Rate HEP Detectors at HL-LHC [C] . S. Panati, A. Paterno, E. Monteil, IEEE Nuclear Science Symposium . 2016

机译：HL-LHC在65nm CMOS中为65nm CMOS中的新一代像素读出ASIC的第一次测量
5. On-chip spatial image processing with CMOS active pixel sensors. [D] . Hong, Canaan Sungkuk. 2001

机译：使用CMOS有源像素传感器的片上空间图像处理。
6. A 4.8-μVrms-Noise CMOS-Microelectrode Array With Density-Scalable Active Readout Pixels via Disaggregated Differential Amplifier Implementation [O] . Jun Ogi, Yuri Kato, Yusaku Nakashima, 2010

机译：通过分解差分放大器实现具有密度可缩放的有源读出像素的4.8μVrms噪声CMOS微电极阵列
7. First Measurements of a Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for Extreme Rate HEP Detectors at HL-LHC [O] . Panati, Serena, Paternò, Andrea, Monteil, Ennio, 2016

机译：HL-LHC上用于极速HEP检测器的65 nm CMOS新一代像素读出ASIC原型的首次测量

Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

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