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首页> 外文期刊>IEEE Transactions on Nuclear Science >Design of a Real-Time FPGA-Based Data Acquisition Architecture for the LabPET II: An APD-Based Scanner Dedicated to Small Animal PET Imaging
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Design of a Real-Time FPGA-Based Data Acquisition Architecture for the LabPET II: An APD-Based Scanner Dedicated to Small Animal PET Imaging

机译：LabPET II的基于FPGA的实时数据采集架构设计：基于APD的小动物PET成像专用扫描仪

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The LabPET II detector block was designed to achieve submillimeter spatial resolution in small animal PET imaging. Each detection block consists of two arrays of 4$, times,$8 avalanche photodiodes (APD) individually coupled to an 8$, times,$ 8 scintillator array, to form 64 independent detectors with parallel readout channels. This new detection block entails an eightfold increase in pixel density compared to the LabPET I. A 64-channel mixed-signal application-specific integrated circuit (ASIC) was designed to extract relevant PET data in real time from the LabPET II detection blocks. In order to interface the ASICs forming the PET camera with the storage units, a real-time FPGA-based digital data acquisition (DAQ) system was designed. The DAQ system allows event harvesting, processing and transmission to a host computer for data storage as well as system programming and calibration. Real-time event processing embedded in the DAQ includes time trigger, energy computation using a time-over-threshold (TOT) conversion scheme, timing corrections, and event sorting trees. In the standard DAQ mode, a real-time coincidence engine analyzes events and only keeps relevant information to minimize data throughput and post-acquisition data processing. The architecture consists of three FPGA-based electronic layers wired through gigabit links: a Front-End layer extracts time and energy along with the pixel address, a custom Hub layer chronologically sorts incoming events, and a Coincidence engine matches coincident events and computes an estimate of the random events rate. Every FPGA in the different layers is accessible through an Ethernet link. The real-time digital architecture sustains the required throughput of $sim $111 million events/s for a $sim {hbox{37thinspace000}}$-channel scanner configuration.
机译：LabPET II检测器模块设计用于在小动物PET成像中实现亚毫米级的空间分辨率。每个检测块由两个分别由8个雪崩光电二极管（APD）耦合的8个雪崩光电二极管（APD）组成的两个阵列组成，每个阵列分别是4 $公式Formulatype =“ inline”> $，times，$ 8个闪烁器阵列，以形成64个具有并行读出通道的独立检测器。与LabPET I相比，这种新的检测模块的像素密度增加了八倍。设计了64通道混合信号专用集成电路（ASIC），以从LabPET II检测模块实时提取相关的PET数据。为了使构成PET相机的ASIC与存储单元连接，设计了基于FPGA的实时数字数据采集（DAQ）系统。 DAQ系统允许事件收集，处理和传输到主机以进行数据存储以及系统编程和校准。嵌入在DAQ中的实时事件处理包括时间触发，使用阈值时间（TOT）转换方案的能量计算，定时校正和事件排序树。在标准DAQ模式下，实时重合引擎将分析事件，并且仅保留相关信息，以最大程度地减少数据吞吐量和采集后的数据处理。该架构包含通过千兆链路链接的三个基于FPGA的电子层：前端层提取时间和能量以及像素地址，自定义集线器层按时间顺序对传入事件进行排序，并且重合引擎匹配重合事件并计算估计值随机事件发生率。通过以太网链路可以访问不同层中的每个FPGA。实时数字体系结构可为 $ sim $ 1.11亿个事件/秒的吞吐量。内联”- $ sim {hbox {37thinspace000}} $ -通道扫描器配置。

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