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首页> 外文期刊>IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control >Design and analysis of a K-band low-phase-noise phase-locked loop with subharmonically injection-locked technique
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Design and analysis of a K-band low-phase-noise phase-locked loop with subharmonically injection-locked technique

机译：次谐波注入锁相技术的K波段低相位噪声锁相环的设计与分析

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摘要

In this paper, we present design and analysis of a K-band (18 to 26.5 GHz) low-phase-noise phase-locked loop (PLL) with the subharmonically injection-locked (SIL) technique. The phase noise of the PLL with subharmonic injection is investigated, and a modified phase noise model of the PLL with SIL technique is proposed. The theoretical calculations agree with the experimental results. Moreover, the phase noise of the PLL can be improved with the subharmonic injection. To achieve K-band operation with low dc power consumption, a divide-by-3 injection-locked frequency divider (ILFD) is used as a frequency prescaler. The measured phase noise of the PLL without injection is -110 dBc/Hz at 1 MHz offset at the operation frequency of 23.08 GHz. With the subharmonic injection, the measured phase noises at 1 MHz offset are -127, -127, and -119 dBc/Hz for the subharmonic injection number NINJ = 2, 3, and 4, respectively. Moreover, the performance of the proposed PLL with and without SIL technique can be compared with the reported advanced CMOS PLLs.
机译：在本文中，我们使用亚谐波注入锁定（SIL）技术介绍了K波段（18至26.5 GHz）的低相位噪声锁相环（PLL）的设计和分析。研究了具有次谐波注入的PLL的相位噪声，并提出了一种采用SIL技术的PLL的修正相位噪声模型。理论计算与实验结果吻合。此外，通过次谐波注入可以改善PLL的相位噪声。为了实现低直流功耗的K波段操作，将三分频注入锁定分频器（ILFD）用作频率预分频器。在23.08 GHz的工作频率下，在1 MHz偏移下，未注入的PLL的测量相位噪声为-110 dBc / Hz。对于次谐波注入，对于次谐波注入数NINJ = 2、3和4，在1 MHz偏移处测得的相位噪声分别为-127，-127和-119 dBc / Hz。此外，可以将所建议的具有和不具有SIL技术的PLL的性能与已报道的高级CMOS PLL进行比较。

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