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首页> 外文期刊>IEICE Transactions on Information and Systems >Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme
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Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme

机译：同时进行舍入方案的支持格式转换和舍入运算的浮点加法器的设计

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摘要

The format conversion operations between a floating-point number and an integer number and a round operation are the important standard floating-point operations. In most eases, these operations are implemented by adding additional hardware to the floating-point adder. The SR (simultaneous rounding) method, one of the techniques used to improve the performance of the floating-point adder, can perform addition and rounding operations at the same stage and is an efficient method with respect to the silicon area and its performance. In this paper, a hardware model to execute CRops (conversion and rounding operations) for the SR floating-point adder is presented and CRops are analyzed on the proposed hardware model. Implementation details are also discussed. The proposed scheme can maintain the advantages of the SR method and can perform each CRop with three pipeline stages.
机译：浮点数和整数之间的格式转换操作以及舍入运算是重要的标准浮点运算。在大多数情况下，这些操作是通过向浮点加法器添加其他硬件来实现的。 SR（同时取整）方法是一种用于提高浮点加法器性能的技术，可以在同一阶段执行加法和取整操作，对于硅面积及其性能而言，这是一种有效的方法。本文提出了一种用于执行SR浮点加法器的CRop（转换和舍入运算）的硬件模型，并在提出的硬件模型上分析了CRops。还讨论了实现细节。提出的方案可以保持SR方法的优势，并且可以在三个流水线阶段执行每个CRop。

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