To implement high-speed panoramic unwrapping of high-resolution catadioptric omnidirectional images on field-programmable gate array (FPGA), a novel design technique of pipeline architecture is proposed, named a `series' parallel pipeline'. Based on the strategy of `block prefetching', catadioptric omnidirectional images are divided into image blocks before loading into the pipeline. Multiple functional sub-modules are copied to carry out the relatively time-consuming steps in parallel whereas fewer sub-modules or only one sub-module is created to carry out those less time-consuming steps. The number of copies is determined by the proportion of execution time of each step, and several neighbouring basic units are combined to form a `unit package' before loading into the pipeline. The basic units in one 'unit package' are processed in series while carrying out the less time-consuming steps, but processed in parallel while carrying out the more time-consuming steps. A hardware pipeline design of series¿parallel architecture is implemented on Xilinx Spartan-3 FPGA, which is able to unwrap one catadioptric omnidirectional image with size 1024 x 1024 into one cylindrical panorama with size 3200 x 768 at 12.480 ms per frame when the system clock is 100 MHz.
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机译：为了在现场可编程门阵列（FPGA）上实现高分辨率折反射全向图像的高速全景展开，提出了一种新的流水线架构设计技术，称为“串联”并行流水线。基于“块预取”策略，折反射全向图像在装入管道之前被分为图像块。复制多个功能子模块以并行执行相对耗时的步骤，而创建更少的子模块或仅创建一个子模块来执行那些耗时较少的步骤。副本的数量由每个步骤的执行时间比例决定，在加载到管道中之前，将几个相邻的基本单元组合在一起以形成一个“单元包”。一个“单元包装”中的基本单元在执行耗时较少的步骤的同时进行串行处理，而在执行耗时较多的步骤的同时进行并行处理。在Xilinx Spartan-3 FPGA上实现了串行并行架构的硬件流水线设计，当系统时钟为每帧12.480 ms时，它能够将一张1024 x 1024的折反射全向图像展开为一张3200 x 768的圆柱全景图。是100 MHz。
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