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Embedded System for Biometric Online Signature Verification

机译:用于生物特征在线签名验证的嵌入式系统

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This paper describes the implementation on field-programmable gate arrays (FPGAs) of an embedded system for online signature verification. The recognition algorithm mainly consists of three stages. First, an initial preprocessing is applied on the captured signature, removing noise and normalizing information related to horizontal and vertical positions. Afterwards, a dynamic time warping algorithm is used to align this processed signature with its template previously stored in a database. Finally, a set of features are extracted and passed through a Gaussian Mixture Model, which reveals the degree of similarity between both signatures. The algorithm was tested using a public database of 100 users, obtaining high recognition rates for both genuine and forgery signatures. The implemented system consists of a vector floating-point unit (VFPU), specifically designed for accelerating the floating-point computations involved in this biometric modality. Moreover, the proposed architecture also includes a microprocessor, which interacts with the VFPU, and executes by software the rest of the online signature verification process. The designed system is capable of finishing a complete verification in less than 68 ms with a clock rated at 40 MHz. Experimental results show that the number of clock cycles is accelerated by a factor of $times$4.8 and $times$11.1, when compared with systems based on ARM Cortex-A8 and when substituting the VFPU by the Floating-Point Unit provided by Xilinx, respectively.
机译:本文介绍了用于在线签名验证的嵌入式系统的现场可编程门阵列(FPGA)的实现。识别算法主要包括三个阶段。首先,对捕获的签名进行初始预处理,以去除噪声并标准化与水平和垂直位置有关的信息。然后,使用动态时间规整算法将该处理后的签名与其先前存储在数据库中的模板对齐。最后,提取一组特征并通过高斯混合模型,该模型揭示了两个特征之间的相似程度。使用100个用户的公共数据库对该算法进行了测试,从而获得了真实和伪造签名的高识别率。所实现的系统由向量浮点单元(VFPU)组成,该向量专门设计用于加速此生物特征形式所涉及的浮点计算。此外,所提出的架构还包括微处理器,该微处理器与VFPU交互,并通过软件执行其余的在线签名验证过程。设计的系统能够以68 MHz的时钟在不到68 ms的时间内完成完整的验证。实验结果表明,与基于ARM Cortex-A8的系统相比,以及分别由Xilinx提供的浮点单元代替VFPU时,时钟周期的数量分别提高了$ times $ 4.8和$ times $ 11.1。

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