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Analysis and Suppression of Alias in Digitally Controlled Inverters

机译：数控变频器中的别名分析与抑制

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摘要

In digitally controlled inverters, the output voltage and current contain high-frequency harmonics due to the switching process. Unfortunately, the sampling frequency is often less than twice the bandwidth of measurement signal. Then, the aliasing phenomenon is brought into the sampling process and some low-frequency alias signals which cause power quality deterioration are produced. This paper presents a quantitative analysis to reveal the characteristic of the aliasing phenomenon in digitally controlled inverters. Specifically, the magnitude of alias signal will drop to zero and the phase will be inversed with some special sampling delays. Two alias suppression methods are then proposed by controlling the sampling delay. Steady-state error and low-frequency harmonics are significantly decreased with the proposed methods. The proposed methods have little delay so that the system has a better dynamic performance. The theoretical analysis and alias suppression strategies are validated by experimental results.
机译：在数字控制的逆变器中，由于开关过程，输出电压和电流包含高频谐波。不幸的是，采样频率通常小于测量信号带宽的两倍。然后，将混叠现象带入采样过程，并产生一些引起电能质量下降的低频混叠信号。本文提出了定量分析，以揭示数控逆变器中混叠现象的特征。具体来说，混叠信号的幅度将降为零，并且相位将被反转，并带有一些特殊的采样延迟。通过控制采样延迟，提出了两种混叠抑制方法。所提出的方法可以显着降低稳态误差和低频谐波。所提出的方法几乎没有延迟，因此系统具有更好的动态性能。实验结果验证了理论分析和混叠抑制策略的有效性。

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