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A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation

机译：具有相噪消除功能的delta sigma分数N分频PLL频率合成器中的恒定环路带宽

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摘要

This work presents the design of a new and unique design technique of constant loop bandwidth and phase noise cancellation in a wideband Delta Sigma fractional-N PLL frequency synthesizer. Phase noise performance of the proposed Delta Sigma fractional-N PLL frequency synthesizer has been verified using CppSim simulator with the help of transistor level simulation results in Cadence SpecctreRF. Transient response of the proposed Delta Sigma fractional-N PLL has been verified in transistor level simulation using Cadence SpectreRF in 0.13 mu m standard CMOS process. The proposed phase-noise cancellation and constant loop bandwidth in wideband Delta Sigma fractional-N PLL reduces the out of band phase noise by 18 dBc/Hz at 2 MHz offset frequency for a closed loop bandwidth of 1 MHz, when I-CP,I-max is equal to 2.6 mA. PLL locking time has been reduced with phase noise cancellation and a constant loop bandwidth calibration circuits using the proposed CP unit current cell for the mismatch compensated PFD/DAC in wideband Delta Sigma fractional-N PLL frequency synthesizer. Optimum phase noise performance can be achieved with the help of proposed design technique. Proposed Delta Sigma fractional-N PLL frequency synthesizer is locked within 14.0 mu s with an automatic frequency control circuit of the LC VCO and a constant loop bandwidth calibration circuit through the use of proposed CP unit current cell for the mismatch compensated PFD/DAC for the phase-noise cancellation in worst case condition of K-VFC = 10 and k(LBC) = 150. Our new design technique can be extensively integrated for wideband fractional N PLL for new type of wireless communication paradigm using the thinnest channel subharmonic transistor and low power devices, and it has the potential to open a new era of fractional-N PLLs for wideband application.
机译：这项工作提出了一种新颖独特的设计技术，该技术在宽带Delta Sigma分数N PLL频率合成器中实现恒定环路带宽和相位噪声消除的设计。借助于Cadence SpecctreRF中的晶体管级仿真结果，已使用CppSim模拟器验证了拟议的Delta Sigma分数N PLL频率合成器的相位噪声性能。拟议中的Delta Sigma分数N PLL的瞬态响应已在Cadence SpectreRF的0.13μm标准CMOS工艺的晶体管级仿真中得到了验证。当I-CP，I时，在1 MHz的闭环带宽下，宽带Delta Sigma分数N PLL中建议的相位噪声消除和恒定环路带宽可将带外相位噪声在2 MHz偏移频率下降低18 dBc / Hz。 -max等于2.6 mA。 PLL锁定时间已通过相位噪声消除和恒定环路带宽校准电路而减少，该电路使用建议的CP单位电流单元用于宽带Delta Sigma分数N PLL频率合成器中的失配补偿PFD / DAC。借助建议的设计技术可以实现最佳的相位噪声性能。拟议的Delta Sigma分数N分频PLL频率合成器通过使用LC VCO的自动频率控制电路和恒定环路带宽校准电路在14.0μs内锁定，方法是使用建议的CP单位电流单元为失配补偿的PFD / DAC进行锁定。在K-VFC = 10和k（LBC）= 150的最坏情况下消除相位噪声。我们的新设计技术可以使用最薄的信道亚谐波晶体管和低噪声，广泛集成到宽带分数N PLL，以用于新型无线通信范例。功率器件，它有可能为宽带应用开启小数N分频PLL的新时代。

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