...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Integration >Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems
【24h】

Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems

机译：基于FPGA的动态部分可重新配置系统的系统分区多目标设计空间探索

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification.
机译：动态部分重新配置（DPR）启用基于FPGA的系统中的资源共享。它还可以通过增加冗余部分可重新配置的区域（PRRS）的数量来减轻衰老相关的永久性故障。通常，这些PRR能够在一个特定实例上托管任何部分可重构的模块（PRMS）或任务。这种系统被称为均匀。然而，FPGA资源约束限制了可以使用的均匀冗余量，因此影响系统的寿命。可以通过利用异构方法来解决此问题，其中每个PRR现在只托管任务的子集。此外，还必须在设计阶段处理应用程序的截止日期，以确定对PRR的任务的映射和调度。为此，我们提出了一种特定于应用的多目标系统级设计方法，以确定适当数量的PRR和PRRS的映射和调度。具体地，我们提出了一种寿命感知的调度方法，可以最大化系统的平均故障（MTTF）在应用程序的Makespan规范中具有不同公差。我们使用Scheduler以及一个自动平面图用于在设计时设计空间探索，以产生可行的异构PRR基系统。我们的实验表明，异构系统可以提供超过2倍的终身改善。它还提供了更好的缩放，并在Mapespan规范中具有更高的耐受性。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号