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Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications

机译:用于千兆无线通信的低复杂性多模式多路分层分层LDPC解码器

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摘要

This paper presents a novel low-complexity multi-mode multi-way split-row (split by factors of 2, 4, and 8) partially parallel pipelined layered low-density parity-check (LDPC) decoder architecture that is suitable for gigabit wireless communications. The innovative feature of the proposed decoder is related to the multi-way split row layered LDPC decoding algorithm and architecture design techniques. Furthermore, we employed an efficient parity-check matrix-reordering method that uses row reordering, column reordering, and a local switching network to develop a multi-mode decoder that can support all four code rates specified in the IEEE 802.11ad standard. The proposed decoder can effectively reduce the complexity by a factor that is equal to the splitting factor, while the effect on the overall error-performance loss is negligible. Post-synthesis implementation results on TSMC 40-nm CMOS technology show that the proposed approach achieves higher area efficiency (throughput-to-area ratio) compared with other related previous works. For all four code rates, the proposed split-row pipe lined layered LDPC decoder architecture (s = 2) occupies an area of 0.168 mm(2) and achieves an encoded throughput of 11.8 Gb/s at five decoding iterations.
机译:本文介绍了一种新型低复杂性多模式多路拆分行(由2,4和8)的部分分开部分并行流水线分层低密度奇偶校验(LDPC)解码器架构,适用于千兆无线通讯。所提出的解码器的创新特征与多路分开分层LDPC解码算法和架构设计技术有关。此外,我们使用了一种有效的奇偶校验矩阵重新排序方法,该重新排序方法使用行重新排序,列重新排序和本地交换网络来开发一个多模式解码器,可以支持IEEE 802.11ad标准中指定的所有四个码率。所提出的解码器可以通过等于分裂因子的因子有效地降低复杂性,而对整体误差性能损失的影响可以忽略不计。综合后实现TSMC 40-NM CMOS技术的结果表明,与其他相关的先前作品相比,该方法达到了更高的区域效率(吞吐量与面积比率)。对于所有四个代码率,所提出的分体式管道衬里分层LDPC解码器架构(S = 2)占据0.168mm(2)的面积,并在五个解码迭代中实现了11.8 Gb / s的编码吞吐量。

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