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FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm

机译：FPGA实现高性能，资源高效的基数-16基于CORDIC旋转器的FFT算法

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The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (CORDIC) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, CORDIC needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 CORDIC algorithm takes n/4 iteration as compared to n iteration of the radix-2 CORDIC algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex-7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.
机译：快速傅里叶变换（FFT）是一种算法，广泛用于计算实时数字信号处理中的离散傅里叶变换（DFT）。对于任何实时应用，都非常希望资源较少的高性能。我们所提出的工作介绍了基于FPGA设备上修改的前馈双路径延迟换向器（DDC）架构的基于修改的前馈双路径延迟换向器（DDC）架构的RADIX-2抽取频率（R2DIF）FFT算法。需要一个复杂的乘法器来执行复杂的旋转因子和大存储器来存储旋转因子是FFT实现的主要问题。建议工作旨在解决这些问题。在这项工作中，提出了一种高性能的基数-16坐标旋转数字计算机（CORDIC）算法的旋转器，以执行复杂的旋转因子倍增。此外，CORDIC仅需要旋转角度来执行复杂的乘法，这减少了对大存储器来存储滑动因子的需要。为了计算N比特精度的总旋转，我们所提出的基数-16 CORDIC算法与NATIX-2 CORDIC算法的N迭代相比需要n / 4迭代。我们在Virtex-7系列FPGA上实现了我们的RADIX-2抽取频率（R2DIF）算法的建筑。此外，我们提出的FFT实现和最近提出的FFT实现之间的详细比较。实验结果表明，与最近提出的实施相比，建议实施具有较少的延迟和硬件利用率。

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