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On the superiority of modularity-based clustering for determining placement-relevant clusters

机译：关于基于模块化的聚类的优越性，确定放置相关簇

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摘要

In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies it would be very valuable to better predict final placement of the gate-level netlist: this would enable more accurate early assessment of performance, congestion and floorplan viability in the SOC floorplanning/RTL planning stages of design. In this work, we study a new criterion for the classic challenge of VLSI netlist clustering: how well netlist clusters "stay together" through final implementation. We propose the use of several evaluators of this criterion. We also explore the use of modularity-driven clustering to identify natural clusters in a given graph without the tuning of parameters and size balance constraints typically required by VLSI CAD partitioning methods. We find that the netlist hypergraph-to-graph mapping can significantly affect quality of results, and we experimentally identify an effective recipe for weighting that also comprehends topological proximity to I/Os. Further, we empirically demonstrate that modularity-based clustering achieves better correlation to actual netlist placements than traditional VLSI CAD methods (our method is also 2x faster than use of hMetis for our largest testcases). Finally, we propose a flow with fast "blob placement" of clusters. The "blob placement" is used as a seed for a global placement tool that performs placement of the flat netlist. With this flow we achieve 20% speedup on the placement of a netlist with 4.9 M instances with less than 3% difference in routed wirelength.
机译：在先进的技术节点中，IC实施面临着越来越多的设计复杂性以及更苛刻的设计计划要求。这提出了对新的分解方法，可以帮助降低问题复杂性的新分解方法，结合新的预测方法，可以帮助避免物理实现流程中的瓶颈和循环。值得注意的是，通过现代设计方法，更好地预测门级网表的最终放置是非常有价值的：这将使在SOC PlacePlanning / RTL规划阶段的SOC PlacePlanning / RTL规划阶段中的性能，拥塞和地板可行性更准确地评估。在这项工作中，我们研究了VLSI NetList聚类经典挑战的新标准：NetList集群通过最终实施方式如何群众群“在一起”。我们提出了使用本标准的几个评估人员。我们还探讨了模块化驱动群集的使用，以识别给定图中的自然簇，而不会调整VLSI CAD分区方法通常需要的参数和大小余额约束。我们发现网表超图形到图形映射可以显着影响结果的质量，我们通过实验确定了一个有效的加权配方，也可以理解I / O的拓扑接近度。此外，我们经验证明了基于模块化的聚类与传统的VLSI CAD方法相比，与实际的网表展示率更好地相关（我们的方法也比我们最大的测试酶的使用比HMETIS快2倍）。最后，我们提出了一种流动的簇的快速“布布放置”。 “Blob Playement”用作用于整体放置工具的种子，该工具执行扁平网表的放置。通过这种流程，我们在将4.9米实例的位置放置有20％的快速加速，在4.9米的情况下，路由线长差异小于3％。

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  • 来源
    《Integration》 |2020年第9期|32-44|共13页
  • 作者

    Fogaca Mateus; Kahng Andrew B.; Monteiro Eder; Reis Ricardo; Wang Lutong; Woo Mingyu;

  • 作者单位

    Univ Fed Rio Grande do Sul Inst Informat PGMicro Porto Alegre RS Brazil|Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil;

    Univ Calif San Diego CSE La Jolla CA 92093 USA|Univ Calif San Diego ECE Dept La Jolla CA 92093 USA;

    Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil;

    Univ Fed Rio Grande do Sul Inst Informat PGMicro Porto Alegre RS Brazil|Univ Fed Rio Grande do Sul Inst Informat PPGC Porto Alegre RS Brazil|Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil;

    Univ Calif San Diego ECE Dept La Jolla CA 92093 USA;

    Univ Calif San Diego ECE Dept La Jolla CA 92093 USA;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    EDA; Physical design; Floorplanning; Placement; Modularity-based clustering;

    机译：EDA;物理设计;地板;放置;基于模块化的聚类;

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