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Yield constrained automated design algorithm for power optimized pipeline ADC

机译：电力优化管道ADC产量约束自动化设计算法

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摘要

Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit pipeline ADC is designed and analyzed. This ADC has 10-bit resolution and 6.3 mW power, 91% yield, 55.3 dB SNDR and 58.8 dB SFDR, which are all in good agreement with the algorithm results. In comparison with similar designs it offers a competitive Figure of Merit (FOM), which proves the capability of this algorithm in finding the optimum solution.
机译：管道模数转换器（ADC）设计过程包括几个重新设计的步骤，以实现最佳解决方案。因此，设计人员喜欢为此目的使用自动化算法。在本文中，考虑了对流水线ADC的产量和功耗之间的折衷来提出了一种CAD工具的自动化算法。这种自动化算法从多次自由中受益，包括系统级别到晶体管级参数，这有助于CAD工具找到优化的解决方案。它允许设计人员在屈服和功耗之间进行权衡选择最佳场景。为了评估该算法的能力，设计并分析了10位管线ADC。该ADC具有10位分辨率和6.3 MW功率，91％的收益率，55.3个DB SNDR和58.8 dB SFDR，这一切都与算法结果良好。与类似的设计相比，它提供了竞争优异（FOM）的竞争性图，这证明了该算法在找到最佳解决方案时的能力。

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