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SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage

机译：近阈值电压的高产量和节能存储器操作的SRAM片上监测方法

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摘要

Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, V-ddmin, on each die that does not cause SRAM read and write failures, which are majorities of SRAM failures, under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, V-fail, that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM (V) over cap (ddmin) on each die from the measured V-fail of SRAM monitor on the same die where V-fail-V-ddmin correlation table is built-up in design infra development phase, and (V) over cap (ddmin) can be directly derived from the measured Vfail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 10.45%, read energy by 4.99%, and write energy by 5.45% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint. In addition, the effect of IR drop and process variations of peripheral circuit on V-ddmin prediction is taken into account by reflecting them on SRAM bitcell operation. We also solidify our V-ddmin prediction methodology by considering the prevention of potential SRAM access failures for high-speed designs as well as the SRAM read and write failures.
机译：通过近阈值电压（NTV）操作的低功率设计非常有吸引力，因为它提供了显着减轻功率耗散的急剧增加。然而，用于使用NTV操作的一个关键屏障是SRAM故障的显着增加。在这项工作中，我们提出了一种片上SRAM监测方法，可以准确地预测每个芯片上的最小电压V-DDMIN，这些模具不会导致SRAM读写的错误，这些故障是目标的多数SRAM故障，在目标下置信水平。精确地，我们提出了一个SRAM监视器，我们测量最大电压V-FAIL，导致该SRAM监视器上的功能失败。然后，我们提出了一种新颖的，在同一模具上测量的V-D-DDMIN相关表在设计中，在SRAM监视器上的测量V-DICK OV-D-DDMIN相关表中的测量V-DICK，在每个模具上提出了一种新的帽（DDMIN）的新方法。在帽（DDMIN）上的红外线发育阶段和（v）可以直接从引用硅生产阶段中的相关表的测量vFail。通过实验，我们确认我们的提出方法能够将泄漏功率储存10.45％，读取能量为4.99％，并在SRAM比特电池阵列中在SRAM比特电池阵列中将能源置于5.45％，通过对所有模具施加均匀的最小电压而相同产量约束。另外，通过在SRAM位单元操作上反射它们，考虑了IR D降和处理外围电路对V-DDMIN预测的影响。我们还通过考虑预防高速设计的潜在SRAM访问失败以及SRAM读取和写入故障来巩固V-DDMIN预测方法。

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