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Energy Efficient BEC Modified Carry Select Adder based PTMAC Architecture for Biomedical Processors

机译:节能型BEC改进的基于携带选择加法器的PTMAC体系结构,用于生物医学处理器

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Power dissipation is considered as the critical objective in the design of integrated circuits. Concern has increased in the design of adders, which form the basic computational block of any circuit. Research work has been carried out towards the efficient design and performance analysis of Carry Select Adder. Carry Select Adder (CSLA) is used in many data processors to increase the speed of mathematical calculation. The main aim of this paper is to reduce the power by using Binary to Excess-1 Converter, which uses an uncomplicated and proficient gate-level adaptation to reduce the power and area of the Carry Select Adder to a tolerant level. Based on the analysis, the proposed design proves to be better than the Conventional CSLA, BEC Modified Carry Select Adder and the Regular Square Root CSLA. Moreover, the Programmable Truncated Multiplier and Accumulator Circuit architecture designed using the BEC modified CSLA can be used for low power biomedical instrumentation with a need for reticent digital signal processing like ECG fall detection, EEG filtering and others. The BEC modified CSLA has been proven efficient through its implementation in a DSP architecture with the combined benefit of fault tolerant.
机译:功耗被认为是集成电路设计中的关键目标。加法器的设计越来越引起人们的关注,加法器构成任何电路的基本计算模块。已经进行了有关进行携带选择加法器的有效设计和性能分析的研究工作。进位选择加法器(CSLA)用于许多数据处理器中,以提高数学计算的速度。本文的主要目的是通过使用Binary to Excess-1转换器来降低功耗,该转换器使用了简单而精通的门级自适应技术来将进位选择加法器的功耗和面积减小到容忍的水平。在分析的基础上,提出的设计被证明比传统的CSLA,BEC修改的进位选择加法器和规则平方根CSLA更好。此外,使用BEC改进的CSLA设计的可编程截断乘法器和累加器电路体系结构可用于低功耗生物医学仪器,需要进行无声的数字信号处理,例如ECG跌落检测,EEG滤波等。通过在DSP架构中实现BEC修改后的CSLA,已证明是高效的,并且具有容错的综合优势。

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