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首页> 外文期刊>International journal of communication systems >Operation reduced low‐density parity‐check decoding algorithms for low power communication systems
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Operation reduced low‐density parity‐check decoding algorithms for low power communication systems

机译:低功耗通信系统的操作简化了的低密度奇偶校验解码算法

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Decoding operation reduction algorithms on min-sum layered low-density parity-check (LDPC) decoders are proposed in this paper. Our algorithm freezes selected operations in high reliable nodes to reduce power while preserving error correcting performance. Both memory accesses and active node switching activities can be reduced. A novel node refresh mechanism reactivates frozen nodes to minimize coding gain degradation. We propose three decoding operation reduction algorithm variations to trade-off complexity and operation reduction for LDPC decoders with different degrees of parallelism and memory requirement. Simulation results show that the number of LDPC decoding operations is reduced across all SNR ranges. The decoding convergence speed is not affected. Hardware architecture and FPGA implementation for IEEE 802.16e LDPC codes are presented. Copyright © 2011 John Wiley & Sons, Ltd.
机译:提出了最小和分层低密度奇偶校验(LDPC)解码器上的解码操作减少算法。我们的算法将选定的操作冻结在高度可靠的节点中,以降低功耗,同时保留纠错性能。可以减少内存访问和活动节点切换活动。一种新颖的节点刷新机制可重新激活冻结的节点,以最大程度地减少编码增益降级。针对不同并行度和存储要求的LDPC解码器,我们提出了三种解码操作减少算法的变体,以权衡复杂性和操作减少。仿真结果表明,在所有SNR范围内,LDPC解码操作的数量均减少了。解码收敛速度不受影响。介绍了用于IEEE 802.16e LDPC代码的硬件架构和FPGA实现。版权所有©2011 John Wiley&Sons,Ltd.

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