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首页> 外文期刊>International journal of computer science and network security >FPGA-based Implementation of Digital Logic Design using Altera DE2 Board
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FPGA-based Implementation of Digital Logic Design using Altera DE2 Board

机译：使用Altera DE2板实现基于FPGA的数字逻辑设计

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In control applications, most of the physical systems require a real-time operation to interface high speed constraints; higher density programmable logic devices such as field programmable gate array (FPGA) can be used to integrate large amounts of logic in a single IC. This paper presents an Experimental implementation of digital logic designs on the Altera DE2 board which presented as an educational and development board, in order to check the flexible implementation with FPGA and to get the better and safely ways to use these specifications during any design implementations. The implementation in this paper contains of two types of digital logic design, the first one is Digital UP-counter design which designed using Verilog language, the experimental results for this design was displayed on the 7-segment with the sequence of HEX0 and HEX1. The second design is one-input Digital fuzzy logic controller which contain of three parts, Fuzzifier, inference engine and Defuzzifier. The typical Fuzzy logic controller was designed using VHDL language; the memory block of this design was generated using MegaWizard Plug-in Manager which provided by Altera Quartus II program, the design using MegaWizard is important to ensure the good design specifications. To improve this design, groups of membership function with 5 linguistics variable and rule table of 25 rules were used to generate the control surface of the fuzzy logic controller, and to generate the simulation before the implementation. From these results, we got that the maximum error, minimum error, mean error, mean square error and range of values are: 0.5349, -0.5349, 3.89E-17, 0.0196 and -30 to 30, respectively. These results proved that the FPGA-based fuzzy controller is very close to the software-based controller using MATLAB.
机译：在控制应用中，大多数物理系统都需要实时操作来接口高速约束。诸如现场可编程门阵列（FPGA）之类的更高密度的可编程逻辑器件可用于在单个IC中集成大量逻辑。本文介绍了在Altera DE2板上作为实验和开发板提供的数字逻辑设计的实验实现，目的是检查FPGA的灵活实现并获得在任何设计实现中使用这些规范的更好安全的方法。本文的实现包含两种类型的数字逻辑设计，第一种是使用Verilog语言设计的数字UP计数器设计，该设计的实验结果以HEX0和HEX1的顺序显示在7段中。第二种设计是单输入数字模糊逻辑控制器，它由模糊器，推理机和去模糊器三部分组成。典型的模糊逻辑控制器是使用VHDL语言设计的。该设计的存储模块是使用Altera Quartus II程序提供的MegaWizard插件管理器生成的，因此使用MegaWizard进行设计对于确保良好的设计规格至关重要。为了改进此设计，使用具有5种语言学变量的隶属函数组和25条规则的规则表来生成模糊逻辑控制器的控制面，并在实施之前生成仿真。从这些结果中，我们得出最大误差，最小误差，均值误差，均方误差和值范围分别为：0.5349，-0.5349、3.89E-17、0.0196和-30至30。这些结果证明，基于FPGA的模糊控制器与使用MATLAB的基于软件的控制器非常接近。

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