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首页> 外文期刊>International journal of electronics >A low-power VLSI implementation for fast full-search variable block size motion estimation
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A low-power VLSI implementation for fast full-search variable block size motion estimation

机译：一种用于快速全搜索可变块大小运动估计的低功耗VLSI实现

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Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This article presents a low-power VLSI implementation for VBSME, which employs a fast full-search block-matching algorithm to reduce power consumption, while preserving the optimal motion vectors (MVs). The fast full-search algorithm is based on the comparison of the current minimum sum of absolute difference (SAD) to a conservative lower bound so that unnecessary SAD calculations can be eliminated. We first experimentally determine the specific conservative lower bound of SAD and then implement the fast full-search algorithm in FPGA and 0.18 μrn CMOS technology. To the best of our knowledge, this is the first time that a fast full-search block-matching algorithm is explored to reduce power consumption in the context of VBSME and implemented in hardware. Experiment results show that the proposed design can save power consumption by 45% compared to conventional VBSME designs that give optimal MV based on the full-search algorithms.
机译：可变块大小运动估计（VBSME）成为H.264 / AVC中的新编码技术。本文介绍了一种适用于VBSME的低功耗VLSI实现，该实现采用快速的全搜索块匹配算法来降低功耗，同时保留最佳运动矢量（MV）。快速的全搜索算法基于当前的最小绝对差之和（SAD）与保守的下限的比较，从而可以消除不必要的SAD计算。我们首先通过实验确定SAD的特定保守下限，然后在FPGA和0.18μmCMOS技术中实现快速的全搜索算法。据我们所知，这是首次探索一种快速的全搜索块匹配算法，以降低VBSME上下文中的功耗并在硬件中实现。实验结果表明，与基于全搜索算法提供最佳MV的常规VBSME设计相比，所提出的设计可节省45％的功耗。

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