EFFECTS OF GATE TUNNELING CURRENT ON THE STATIC CHARACTERISTICS OF CMOS CIRCUITS

TlEFENG WU; HEMING ZHANG; HUIYONG Hu

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EFFECTS OF GATE TUNNELING CURRENT ON THE STATIC CHARACTERISTICS OF CMOS CIRCUITS

机译：门极隧穿电流对CMOS电路静态特性的影响

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With the scaling of MOS devices, gate tunneling current increases in exponential with thinner gate oxides, and the static standby power consumption of CMOS circuits is severely affected by the presence of gate tunneling currents. To illustrate the impacts, in this paper, a simpler gate tunneling current theory model by a double integral approach in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness is presented. The simulation results well agree with the theory model proposed in BSIM4- The characteristics of current source inverter composed of ultra-thin gate oxide MOS devices are also studied in detail to analyze its behavior and predict the trends of power dissipated with scaled technology nodes in the effects of gate tunneling current.

机译：随着MOS器件的缩小，栅极隧穿电流随着栅极氧化物的变薄而呈指数增加，并且由于栅极隧穿电流的存在，严重影响了CMOS电路的静态待机功耗。为了说明其影响，本文提出了一种通过双积分方法在超薄栅极氧化物MOS器件中建立更简单的栅极隧穿电流理论模型的方法，该模型的隧穿电流随栅极氧化物厚度的变化而变化。仿真结果与BSIM4中提出的理论模型非常吻合。还详细研究了由超薄栅极氧化物MOS器件组成的电流源逆变器的特性，以分析其行为并预测在按比例缩放技术节点中功率消耗的趋势。栅极隧穿电流的影响。

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来源
《International Journal of Innovative Computing Information and Control》 |2011年第6期|p.3229-3237|共9页
作者
TlEFENG WU; HEMING ZHANG; HUIYONG Hu;
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作者单位

School of Micro-electronics Xidian University Xi'an, P. R. China, School of Information and Electronic Technology Jiamusi University Jiamusi, P. R. China;

School of Micro-electronics Xidian University Xi'an, P. R. China;

School of Micro-electronics Xidian University Xi'an, P. R. China;

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正文语种 eng
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关键词
device simulation; gate tunneling current model; static power consumption; ultra-thin gate oxide;

机译：设备仿真;栅极隧穿电流模型静态功耗超薄栅氧化层;

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2. Estimation of propagation delay considering short-circuit current for static CMOS gates [J] . Hirata A., Onodera H. IEEE Transactions on Circuits and Systems. 1 . 1998,第11期

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3. A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology [J] . Maryan Mohammad Moradinezhad, Amini-Valashani Majid, Azhari Seyed Javad Circuits, systems and signal processing . 2021,第7期

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6. Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits [O] . Yiming Li, Chieh-Yang Chen, Min-Hui Chuang, 2019

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EFFECTS OF GATE TUNNELING CURRENT ON THE STATIC CHARACTERISTICS OF CMOS CIRCUITS

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