...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>International journal of numerical modelling >Increasing I_(ON)/I_(OFF) by embedding a low doped buried layer in the channel of a dual‐material double‐gate junctionless MOSFET
【24h】

Increasing I_(ON)/I_(OFF) by embedding a low doped buried layer in the channel of a dual‐material double‐gate junctionless MOSFET

机译：通过在双材料双栅极无结MOSFET的沟道中嵌入低掺杂掩埋层来增加I_（ON）/ I_（OFF）

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

To suppress the short-channel effects (SCEs) and the OFF-state current (I-OFF) and increasing the ON-state current (I-ON)/I-OFF ratio, the conventional dual-material double-gate (DG) junctionless (JL) metaloxide-semiconductor field effect transistor (MOSFET) is improved by employing the laterally graded channel doping profile and embedding a low-doped buried layer along the center of the channel. The channel is divided into two regions under the gates and the region near the drain has higher doping level, while the buried layer has lower doping concentration than the channel. The characteristics of the proposed device are modeled analytically, simulated and compared with those of the dual-material DGJL MOSFETs with uniformly doped and laterally graded doped channels without the buried layer. The results show that because of using the dual-material gate, the graded doped channel, and the buried layer, the proposed DGJL MOSFET exhibits more improved performance against the SCEs and lower I-OFF. The higher electric field near the source and higher carrier velocity along the channel improve the I-ON and the I-ON/I-OFF ratio of the proposed device, considerably. Also, because of lower subthreshold slope, drain-induced barrier lowering, and gate capacitance, the proposed device exhibits better switching performance than the other considered structures.
机译：为了抑制短沟道效应（SCE）和OFF状态电流（I-OFF）并增加ON状态电流（I-ON）/ I-OFF比，传统的双材料双栅极（DG）通过采用横向渐变的沟道掺杂分布并沿沟道中心嵌入低掺杂掩埋层，可以改善无结（JL）金属氧化物半导体场效应晶体管（MOSFET）。沟道在栅极下方分为两个区域，漏极附近的区域具有较高的掺杂水平，而埋层的掺杂浓度低于沟道。拟议器件的特性经过分析建模，仿真并与具有均匀掺杂和横向渐变掺杂沟道而没有掩埋层的双材料DGJL MOSFET的特性进行了建模和比较。结果表明，由于使用了双材料栅极，渐变掺杂沟道和掩埋层，所提出的DGJL MOSFET相对于SCE具有更好的性能，并且I-OFF更低。源附近的较高电场和沿沟道的较高载流子速度极大地改善了所提出器件的I-ON和I-ON / I-OFF比。而且，由于较低的亚阈值斜率，漏极引起的势垒降低和栅极电容，因此所提出的器件比其他考虑的结构具有更好的开关性能。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号