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首页> 外文期刊>International journal of reconfigurable computing >Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues
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Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues

机译：用于数字电视机顶盒的SoC的开发：体系结构和系统集成问题

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摘要

This work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require large storage capacity and high bandwidth memory. Also, those systems are built from heterogeneous processing units, designed to perform specific tasks in order to maximize the overall system efficiency. A single off-chip memory is generally shared between the processing units to reduce power and save costs. The external memory access is one bottleneck when decoding high-definition video sequences in real time. In this work, a four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The use of the memory hierarchy in the system design is challenging because it impacts the system integration process and IP reuse in a collaborative design team. Practical strategies used to solve integration problems are discussed in this text. The SoC architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board.
机译：这项工作提出了几个IP的集成，以生成符合SBTVD标准的数字电视机顶盒的片上系统（SoC）。用于诸如视频处理系统之类的多媒体应用的嵌入式消费类电子产品需要大存储容量和高带宽内存。而且，这些系统是由异构处理单元构建的，旨在执行特定任务，以使整体系统效率最大化。通常在处理单元之间共享单个片外存储器，以降低功耗并节省成本。实时解码高清视频序列时，外部存储器访问是一个瓶颈。在这项工作中，设计了一个四级内存层次结构，以低延迟的宏块粒度管理解码视频。在系统设计中使用内存层次结构具有挑战性，因为它会影响协作设计团队中的系统集成过程和IP重用。本文讨论了用于解决集成问题的实用策略。 SoC架构已经过验证，并正在使用Xilinx Virtex-5 FPGA板进行逐步原型设计。

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