...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Japanese journal of applied physics >Sub-1-V-60nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell
【24h】

Sub-1-V-60nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

机译：基于Sub-1-V-60nm垂直体沟道MOSFET的六晶体管静态随机存取存储阵列，具有宽的噪声容限和出色的功率延迟乘积，并且通过静态随机存取存储单元的单元比对其进行了优化

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array. (C) 2018 The Japan Society of Applied Physics.
机译：在本研究中，为了实现宽的噪声容限和出色的功率延迟乘积（PDP），评估了基于垂直主体通道（BC）-MOSFET的六晶体管（6T）静态随机存取存储器（SRAM）阵列通过改变SRAM单元的每个部分中的柱数，即通过改变SRAM单元中的单元比率。与基于栅极长度和沟道宽度相同的90 nm平面MOSFET的6T SRAM阵列相比，基于60纳米垂直BC-MOSFET的6T SRAM阵列在最佳PDP下可实现0.84V的操作，并且PDP提升高达31％。与60 nm垂直BC-MOSFET一样。此外，基于BC-MOSFET的垂直6T SRAM阵列实现了8.8％的更大的读取静态噪声容限（RSNM），16％的更大的写入容限（WM）和89％的漏电流。而且，已经表明，改变单元比可以在基于垂直BC-MOSFET的6T SRAM阵列中带来更大的RSNM，WM和写入时间改进。 （C）2018年日本应用物理学会。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号