Design and experimental verification of low-voltage two-dimensional CMOS electrophoresis platform with 32 x 32 sample/hold cell array

Yamaji Yuuki; Niitsu Kiichi; Nakazato Kazuo

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Design and experimental verification of low-voltage two-dimensional CMOS electrophoresis platform with 32 x 32 sample/hold cell array

机译：具有32 x 32采样/保持单元阵列的低压二维CMOS电泳平台的设计和实验验证

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Electrophoresis is widely used in biomedical applications. However, conventional (centimeter-order) electrophoresis requires a high-voltage power supply, which is not suitable for point-of-care testing (POCT). Electrophoresis is driven by electric fields, and miniaturization (from the centimeter order to the micrometer order) is effective for low-voltage operation. A CMOS platform is a cost-competitive and promising candidate for miniaturization and enables the integration of biomolecule manipulation by electrophoresis and its electrochemical sensing. These features will contribute to the development of a biochemical analyzer called the micro-total analysis system (mu-TAS). To realize a truly portable electrophoresis system, we present the design and experimental verification of a low-voltage (<1 V), two-dimensional CMOS electrophoresis platform with 32 x 32 sample/hold cell array. Experimental results showed successful constant voltage outputs to each electrode. By miniaturizing the electrode structure to a 60 mu m pitch, we achieved sufficient electric field strength even at low voltages. (C) 2016 The Japan Society of Applied Physics

机译：电泳广泛用于生物医学领域。但是，常规（厘米级）电泳需要高压电源，这不适用于即时检验（POCT）。电泳是由电场驱动的，小型化（从厘米级到微米级）对于低压操作很有效。 CMOS平台是一种具有成本竞争力且有望实现小型化的平台，并且可以通过电泳及其电化学感应技术整合生物分子操作。这些功能将有助于开发一种称为微量总分析系统（mu-TAS）的生化分析仪。为了实现真正的便携式电泳系统，我们介绍了具有32 x 32采样/保持单元阵列的低压（<1 V）二维CMOS电泳平台的设计和实验验证。实验结果表明，成功地将恒定电压输出到每个电极。通过将电极结构缩小到60μm的间距，即使在低电压下，我们也可以获得足够的电场强度。（C）2016年日本应用物理学会

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《Japanese journal of applied physics》 |2016年第3s2期|03DF07.1-03DF07.7|共7页
作者
Yamaji Yuuki; Niitsu Kiichi; Nakazato Kazuo;
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Nagoya Univ, Grad Sch Engn, Dept Elect Engn & Comp Sci, Nagoya, Aichi 4648603, Japan;

Nagoya Univ, Grad Sch Engn, Dept Elect Engn & Comp Sci, Nagoya, Aichi 4648603, Japan;

Nagoya Univ, Grad Sch Engn, Dept Elect Engn & Comp Sci, Nagoya, Aichi 4648603, Japan;

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1. Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit [J] . Sawigun C., Serdijn W. A. Circuits and Systems I: Regular Papers, IEEE Transactions on . 2011,第7期

机译：低压，低功耗，高精度，AB类电流模式亚阈值CMOS采样和保持电路的分析和设计
2. A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS [J] . Lemmerhirt D.F., Cheng X., White R.D., Ultrasonics, Ferroelectrics and Frequency Control, IEEE Transactions on . 2012,第7期

机译：在标准CMOS中制造的32 x 32电容式微加工超声换能器阵列
3. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS [J] . Gupta Shourya, Gupta Kirti, Calhoun Benton H., IEEE transactions on circuits and systems . I , Regular papers . 2019,第3期

机译：低功耗近阈值10T SRAM位单元，具有增强的与数据无关的读取端口泄漏功能，用于32nm CMOS阵列增强
4. A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm² cell in 32nm high-k metal-gate CMOS [C] . Fujimura Y., Hirabayashi O., Sasaki T., Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 . 2010

机译：具有恒定负电平写缓冲器的可配置SRAM，可在32nm高 k 金属栅CMOS中以0.149µm ^{2 单元进行低压操作}
5. Design and analysis of a 32 x 32-bit database filter chip based on a CMOS compatible photonic VLSI device technology [D] . Tang, Jianjing 2003

机译：基于CMOS兼容光子VLSI器件技术的32 x 32位数据库过滤器芯片的设计和分析
6. P179-M A Verification of Novel Experimental Design for Comparative Two-Dimensional Gel Analysis: Pre-Labeled Samples Fractionated on Anion Exchange Column Followed by 2D DIGE [O] . V. C. Ruddat, P. Beckett, C. R. Rozanas, 2007

机译：P179-M用于比较二维凝胶分析的新颖实验设计的验证：在阴离子交换柱上分馏的预先贴有标签的样品然后进行二维DIGE
7. A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS [O] . Samira Ataei, James E. Stine, Matthew R. Guthaus 2016

机译：具有32nm SOI CMOS中的用于低压操作的64 kB差分单端口12T SRAM设计，用于低压操作

Design and experimental verification of low-voltage two-dimensional CMOS electrophoresis platform with 32 x 32 sample/hold cell array

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