VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images

Hongbo Zhu; Tadashi Shibata

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VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images

机译：带有可配置处理元件阵列的VLSI处理器，用于高分辨率图像中的平衡特征提取

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A VLSI processor employing a configurable processing element array (PEA) is developed for a newly proposed balanced feature extraction algorithm. In the algorithm, the input image is divided into square regions and the number of features is determined by noise effect analysis in each region. Regions of different sizes are used according to the resolutions and contents of input images. Therefore, inside the PEA, processing elements are hierarchically grouped for feature extraction in regions of different sizes. A proof-of-concept chip is fabricated using a 0.18 μm CMOS technology with a 32 × 32 PEA. From measurement results, a speed of 7.5 kfps is achieved for feature extraction in 128 × 128 pixel regions when operating the chip at 45 MHz, and a speed of 55 fps is also achieved for feature extraction in 1920 × 1080 pixel images.

机译：针对新提出的平衡特征提取算法，开发了采用可配置处理元件阵列（PEA）的VLSI处理器。在该算法中，将输入图像划分为正方形区域，并通过每个区域中的噪声效果分析确定特征的数量。根据输入图像的分辨率和内容使用不同大小的区域。因此，在PEA内部，将处理元素按层次进行分组以在不同大小的区域中进行特征提取。使用0.18μmCMOS技术和32×32 PEA制造概念验证芯片。根据测量结果，以45 MHz的频率运行芯片时，在128×128像素区域中的特征提取速度为7.5 kfps，在1920×1080像素图像中的特征提取速度也为55 fps。

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《Japanese journal of applied physics》 |2014年第4s期|04EE05.1-04EE05.7|共7页
作者
Hongbo Zhu; Tadashi Shibata;
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作者单位

VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo 113-0032, Japan;

Center for Innovative Integrated Electronic Systems, Tohoku University, Sendai 980-0845, Japan;

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2. A bit-serial VLSI array processing chip for image processing [J] . Heaton R., Blevins D. IEEE Journal of Solid-State Circuits . 1990,第2期

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4. Recovering faulty processing elements to enhance reliability and lifecycle in VLSI processor arrays [C] . Stroud, C.E., Emmert, . 2001

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5. An efficient digital VLSI neural processing element design for image processing [D] . Chang, Josephine Chia-Fen. 1994

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机译：高分辨率成像雷达实时数据压缩的VLsI处理器设计

VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images

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