Impact of Deformation Potential Increase at Si/SiO_2 Interfaces on Stress-Induced Electron Mobility Enhancement in Metal-Oxide-Semiconductor Field-Effect Transistors

Teruyuki Ohashi; Shunri Oda; Ken Uchida

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Impact of Deformation Potential Increase at Si/SiO_2 Interfaces on Stress-Induced Electron Mobility Enhancement in Metal-Oxide-Semiconductor Field-Effect Transistors

机译：Si / SiO_2界面处变形电势增加对金属氧化物半导体场效应晶体管中应力诱导的电子迁移率增强的影响

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The impact of deformation potential increase at metal-oxide-semiconductor (MOS) interfaces on stress effects is thoroughly studied. In our previous study, we revealed that the deformation potential (D_(ac)) of Si increases at MOS interfaces. The energy split between two- and four-fold valleys is proportional to D_(ac). Therefore, it is considered that the D_(ac) increase at MOS interfaces has an affect on strain effects. D_(ac) effectively changes by adjusting Si-on-insulator (SOI) thickness and carrier distribution at MOS interfaces. Therefore, the SOI thickness dependence and carrier distribution dependence of electron mobility enhancement ratio (△μ_e/μ_e) under strain are investigated. Experimental results are explained by the model including the D_(ac) increase at MOS interfaces. In addition, experimental data are well reproduced by calculation using the position-dependent-D_(ac) model. By applying uniaxial strain, effective mass, subband occupation, and intervalley scattering rate are also changed. Their effects on △μ_e/μ_e are also discussed in this paper.

机译：深入研究了金属氧化物半导体（MOS）界面处的形变电势增加对应力效应的影响。在我们以前的研究中，我们发现Si的变形电位（D_（ac））在MOS界面处增加。在两个和四个折谷之间的能量分配与D_（ac）成正比。因此，可以认为MOS接口处D_（ac）的增加会影响应变效应。 D_（ac）通过调整绝缘体上硅（SOI）的厚度和MOS接口处的载流子分布来有效地改变。因此，研究了应变下电子迁移率提高比（△μ_e/μ_e）的SOI厚度依赖性和载流子分布依赖性。该模型解释了实验结果，其中包括MOS接口处的D_（ac）增加。此外，通过使用与位置相关的D_（ac）模型进行计算，可以很好地再现实验数据。通过施加单轴应变，有效质量，子带占用和音程散射速率也将改变。本文还讨论了它们对△μ_e/μ_e的影响。

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来源
《Japanese journal of applied physics》 |2013年第4issue2期|04CC12.1-04CC12.6|共6页
作者
Teruyuki Ohashi; Shunri Oda; Ken Uchida;
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Department of Physical Electronics, Tokyo Institute of Technology, Megro, Tokyo 152-8552, Japan,Department of Electronics and Electrical Engineering, Keio University, Yokohama 223-8522, Japan;

Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, Megro, Tokyo 152-8552, Japan;

Department of Physical Electronics, Tokyo Institute of Technology, Megro, Tokyo 152-8552, Japan,Department of Electronics and Electrical Engineering, Keio University, Yokohama 223-8522, Japan;

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机译：低于100纳米沟道长度的金属氧化物半导体场效应晶体管的电子速度过冲在77和30 K

Impact of Deformation Potential Increase at Si/SiO_2 Interfaces on Stress-Induced Electron Mobility Enhancement in Metal-Oxide-Semiconductor Field-Effect Transistors

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