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首页> 外文期刊>Japanese journal of applied physics >Low Threshold Voltage and High Mobility N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Using Hf-Si/HfO_2 Gate Stack Fabricated by Gate-Last Process
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Low Threshold Voltage and High Mobility N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Using Hf-Si/HfO_2 Gate Stack Fabricated by Gate-Last Process

机译：采用前栅极工艺制造的Hf-Si / HfO_2栅堆叠的低阈值电压和高迁移率N沟道金属氧化物半导体场效应晶体管

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摘要

Systematic characterization of Hf-Si/HfO_2 gate stacks revealed two mobility degradation modes. One is carrier scattering by fixed charges and/ or trapped charges induced by the crystallization in the thick HfO_2 case (inversion oxide thickness, T_(inv) > 1.6 nm). The other is the Hf penetration into the interfacial layer with the Si substrate in the thin HfO_2 case (T_(inv) < 1.6nm) for the Hf-rich electrode. It was demonstrated that careful optimization of the HfOa thickness and the Hf-Si composition can suppress both modes. As a result, a high electron mobility equivalent to that of n~+polycrystalline silicon (poly-Si)/SiO_2 (248 cm~2 V~(-1) s~(-1) at E_(eff) = 1 MV/cm) was obtained at T_(inv) of 1.47 nm. Moreover, the effective work function of the optimized Hf-Si/HfO_2 gate stack is located within 50 mV from the Si band edge (E_c). An extremely high I_(on) of 1165μA/μm (at I_(off) = 81 nA/ μm) at V_(dd) - 1.0 V was demonstrated for a 45 nm gate n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) without strain enhanced technology.
机译：Hf-Si / HfO_2栅堆叠的系统表征揭示了两种迁移率降低模式。一种是在厚HfO_2情况下（结晶氧化物厚度，T_（inv）> 1.6 nm），固定电荷和/或由结晶引起的俘获电荷引起的载流子散射。另一个是在富Hf电极的薄HfO_2情况下（T_（inv）<1.6nm），Hf渗透到具有Si衬底的界面层中。结果表明，精心优化HfOa厚度和Hf-Si成分可以抑制两种模式。结果，在E_（eff）= 1 MV /时，等效于n〜+多晶硅（poly-Si）/ SiO_2的高电子迁移率（248 cm〜2 V〜（-1）s〜（-1）在1.47nm的T_（inv）处获得。此外，优化的Hf-Si / HfO_2栅堆叠的有效功函数位于距Si带边缘（E_c）50 mV的范围内。对于45 nm栅极N沟道金属氧化物半导体场效应晶体管，在V_（dd）-1.0 V时，I_（on）极高，为1165μA/μm（在I_（off）= 81 nA /μm时） （n-MOSFET）没有应变增强技术。

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  • 来源
    《Japanese journal of applied physics》 |2010年第1issue1期|016502.1-016502.6|共6页
  • 作者

    Takashi Ando; Tomoyuki Hirano; Kaori Tai; Shinpei Yamaguchi; Shinichi Yoshida; Hayato Iwamoto; Shingo Kadomura; Heiji Watanabe;

  • 作者单位

    Department of Material and Life Science, Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871, Japan;

    Semiconductor Technology Development Division, Consumer Products and Device Group, Sony Corporation,4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan;

    Semiconductor Technology Development Division, Consumer Products and Device Group, Sony Corporation,4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan;

    Semiconductor Technology Development Division, Consumer Products and Device Group, Sony Corporation,4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan;

    Semiconductor Technology Development Division, Consumer Products and Device Group, Sony Corporation,4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan;

    Semiconductor Technology Development Division, Consumer Products and Device Group, Sony Corporation,4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan;

    Semiconductor Technology Development Division, Consumer Products and Device Group, Sony Corporation,4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan;

    Department of Material and Life Science, Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871, Japan;

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