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首页> 外文期刊>Japanese journal of applied physics >Excess Capacitance Due to Minority Carrier Injection in CrSi_2/p-Type Crystalline Si Isotype Junction
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Excess Capacitance Due to Minority Carrier Injection in CrSi_2/p-Type Crystalline Si Isotype Junction

机译：CrSi_2 / p型结晶硅同型结中由于少数载流子注入而导致的过量电容

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摘要

Excess current and capacitance phenonema were observed for the first time on a CrSi_2/p-type crystalline silicon junction produced by cathodic arc physical vapor deposition. The heterojunction was investigated by current-voltage-temperature (I-V-T) and capacitance (conductance)-voltage/temperature (C,G-V/T) measurements for the purpose of studying transport and storage features. Excess current, manifested as a crossover at a large forward bias, was observed in I-V-T curves since minority carriers injected into the quasi-neutral region of p-c-Si were neutralized by majority carriers supplied from the p-c-Si semiconductor side. This phenomenon, known as conductivity modulation, appeared distinctly as a hump in C-V/ T curves (storage property); a sharp rise in capacitance towards a maximum value as forward bias increased and the subsequent fall after a specific value. For reverse and low forward bias regions, where minority carrier injection was negligible, geometrical junction capacitance and a shoulder in C-V/T curves were observed. In the voltage range where the peak was observed in C-V/T measurements, trap-assisted tunneling recombination generation and space-charge-limited current (SCLC) mechanisms were determined in the CrSi_2/p-c-Si isotype junction. Traps introduced during tunneling were identified as bulk point defects due to the chromium-boron (Cr-B) complex for the CrSi_2/p-c-Si junction on the Si side by I-V-T and C(G)-T analyses. This finding seemed to be in agreement with a recent DLTS [Deep Level Transient Spectroscopy] measurement in terms of both energy depth (0.26eV) and bulk nature. Finally, the shoulder in C-V/T curves indicated Cr-B point defects in the measurement.
机译：在通过阴极电弧物理气相沉积产生的CrSi_2 / p型晶体硅结上首次观察到过大的电流和电容现象。通过研究电流-电压-温度（I-V-T）和电容（电导）-电压/温度（C，G-V / T）测量异质结，以研究运输和存储特性。在I-V-T曲线中观察到过大的电流，表现为在大的正向偏置处的交叉，这是因为注入p-c-Si准中性区域的少数载流子被从p-c-Si半导体侧提供的多数载流子所中和。这种现象称为电导率调制，在C-V / T曲线中明显表现为驼峰（存储特性）。随着正向偏置的增加，电容急剧增加，并朝着最大值急剧上升，随后在特定值之后下降。对于反向和低正向偏置区域，少数载流子注入可忽略不计，观察到几何结电容和C-V / T曲线的肩部。在C-V / T测量中观察到峰值的电压范围内，在CrSi_2 / p-c-Si同型结中确定了陷阱辅助隧穿重组产生和空间电荷限制电流（SCLC）机制。通过I-V-T和C（G）-T分析，在Si侧CrSi_2 / p-c-Si结处存在铬-硼（Cr-B）络合物，从而将隧穿过程中引入的陷阱识别为体积缺陷。就能量深度（0.26eV）和体积性质而言，这一发现似乎与最近的DLTS [深层瞬态光谱法]测量相符。最后，在C-V / T曲线中的肩部表明了测量中的Cr-B点缺陷。

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  • 来源
    《Japanese journal of applied physics》 |2010年第9issue1期|p.091302.1-091302.8|共8页
  • 作者

    Orhan OEzdemir; U. Deneb Yilmazer; Beyhan Tatar; Mustafa UErgen; Kubilay Kutlu;

  • 作者单位

    Department of Physics, Yildiz Technical University, Esenler/ istanbul, Turkey;

    rnDepartment of Physics, Yildiz Technical University, Esenler/ istanbul, Turkey;

    rnDepartment of Physics, Namik Kemal University, Merkez/ Tekirdag, Turkey;

    rnMaterial Science and Engineering, istanbul Technical University, Maslak/ istanbul, Turkey;

    rnDepartment of Physics, Yildiz Technical University, Esenler/ istanbul, Turkey;

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