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首页> 外文期刊>Japanese journal of applied physics >Electrical Characteristics and Crystal Quality Analysis of Thin-Body (100) Channe Silicon-on-lnsulator Metal-Oxide-Semiconductor Field-Effect Transistors Using Two-Step Elevated Silicon Epitaxial Process
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Electrical Characteristics and Crystal Quality Analysis of Thin-Body (100) Channe Silicon-on-lnsulator Metal-Oxide-Semiconductor Field-Effect Transistors Using Two-Step Elevated Silicon Epitaxial Process

机译：使用两步提升硅外延工艺的薄型（100）Channe绝缘体上硅金属氧化物半导体场效应晶体管的电学特性和晶体质量分析

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摘要

A two-step source/drain elevated epitaxial process for ultra thin fully depleted (FD) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. The relation between the crystal quality of the source/drain extension regions and channel orientation with the silicon epitaxial process is analyzed by transmission electron microscopy (TEM). No defect is observed in the source/ drain extension regions on the (100) channel, whereas crystal defects are observed on the (110) channel. Crystal defect generation in the source/drain extension regions is closely related to channel orientation. Moreover, a low parasitic resistance of thin-body SOI MOSFETs is realized in (100) channel SOI-MOSFET, and high I_(on)(I_(ds))-I_(off) characteristics and the suppression of the roll-off characteristics of thin-body SOI MOSFETs with the (100) channel orientation are shown. It is confirmed that thin-body SOI MOSFETs with a two-step source/drain elevated epitaxial process have a high potential for the application in the 22 nm generation.
机译：提出了一种两步源极/漏极升高的外延工艺，用于超薄完全耗尽型（FD）绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）。通过透射电子显微镜（TEM）分析了源/漏扩展区的晶体质量与硅外延工艺的沟道取向之间的关系。在（100）通道上的源/漏扩展区中未观察到缺陷，而在（110）通道上观察到晶体缺陷。源极/漏极扩展区域中晶体缺陷的产生与沟道取向密切相关。而且，在（100）沟道SOI-MOSFET中实现了薄体SOI MOSFET的低寄生电阻，并且高的I_（on）（I_（ds））-I_（off）特性和抑制滚降特性示出了具有（100）沟道方向的薄体SOI MOSFET的示意图。可以肯定的是，采用两步源/漏增强外延工艺的薄体SOI MOSFET在22 nm世代中具有很高的应用潜力。

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  • 来源
    《Japanese journal of applied physics》 |2009年第4issue2期|205-208|共4页
  • 作者

    Toshiaki Iwamatsu; Takashi Terada; Kozo Ishikawa; Hidekazu Oda; Yasuo Inoue;

  • 作者单位

    Advanced Device Development Department, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan;

    Advanced Device Development Department, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan;

    Renesas Semiconductor Engineering, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan;

    Advanced Device Development Department, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan;

    Advanced Device Development Department, Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan;

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