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首页> 外文期刊>Journal of circuits, systems and computers >Efficient Hardware Implementation of Pseudo-Random Bit Generator Using Dual-CLCG Method
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Efficient Hardware Implementation of Pseudo-Random Bit Generator Using Dual-CLCG Method

机译：使用双CLCG方法的伪随机比特发生器的高效硬件实现

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摘要

In this work, the architecture of a dual-coupled linear congruential generator (dual-CLCG) for pseudo-random bit generation is proposed to improve the speed of the generator and minimize power dissipation with the optimum chip area. To improve its performance, a new pseudo-random bit generator (PRBG) employing two-operand modulo adder and without shifting operation-based dual-CLCG architecture is proposed. The novelty of the proposed dual-CLCG architecture is the designing of LCG based on two-operand modulo adder rather than a three-operand one and without using shifting operation as compared to the existing LCG architecture. The aim of the work is to generate pseudo-random bits at a uniform clock rate at the maximum clock frequency and achieve maximum length of the random bit sequence. The power dissipation with the optimum chip area of PRBG is also observed for the proposed architecture. The generated sequence passes all the 15 tests of the National Institute of Standards and Technology (NIST) standard. Verilog HDL code is used for the design of the proposed architecture. Its simulation is done on commercially available Spartan-3E FPGA (ISE Design Suite by Xilinx) as well as on 90-nm CMOS technology (Cadence tool).
机译：在这项工作中，提出了用于伪随机比特生成的双耦合线性总体增长发电机（双CLCG）的体系结构，以提高发电机的速度，并最大限度地减少与最佳芯片区域的功耗。为了提高其性能，提出了采用双操作数模加法器的新伪随机比特发生器（PRBG），并在不转换基于操作的双CLCG架构的情况下。所提出的双CLCG架构的新颖性是基于双操作数模加法的LCG设计，而不是三个操作数，而不使用换档操作与现有的LCG架构相比。该工作的目的是在最大时钟频率下以统一的时钟速率产生伪随机比特，并实现随机比特序列的最大长度。还观察到具有PRBG的最佳芯片面积的功耗，以便拟议的架构。生成的序列通过了国家标准和技术研究所（NIST）标准的所有15个测试。 Verilog HDL代码用于设计建议的设计。它的仿真是在市售的Spartan-3e FPGA（Xilinx）以及90-NM CMOS技术（Cadence工具）上进行的。

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