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首页> 外文期刊>Journal of cryptographic engineering >Reducing risks through simplicity: high side-channel security for lazy engineers
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Reducing risks through simplicity: high side-channel security for lazy engineers

机译：通过简单性降低风险：懒惰工程师的高侧通道安全性

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摘要

Countermeasures against side-channel attacks are in general expensive, and a lot of research has been devoted to the optimization of their security versus performance trade-off. Besides, a wide literature has also shown that implementing such countermeasures is an error-prone task and requires to deal with various engineering challenges (e.g., physical defaults, compositional errors, ...). This work aims to contribute to this second item, by evaluating the extent to which (almost) key-homomorphic primitives, and in particular a recent PRF instance based on the learning with rounding problem, can lead to easy-to-implement and easier-to-evaluate side-channel-secure designs. We confirm these properties by describing an FPGA implementation that does not require complex (compositional) reasoning in its analysis and can be masked securely under simple design conditions, and for which the evaluation directly scales to arbitrary number of shares. We provide a comprehensive performance and (worst-case) security analysis of our design and compare the obtained results with those of an AES implementation protected with the domain-oriented masking scheme. Results show that simplicity has a cost, which becomes less prohibitive as security requirements increase.
机译：抗侧信道攻击的对策是一般的贵，而且很多研究已经致力于对他们的安全与性能之间权衡的优化。此外，广泛的文献还表明，实施这样的对策是一个容易出错的任务，需要应对各种工程上的挑战（例如，物理默认值，成分错误，...）。这项工作旨在促进这一第二个项目，通过评估的程度（几乎）键同态原语，并基于与四舍五入问题的学习尤其是最近PRF情况下，可能会导致易于实施和easier-到评估侧信道安全的设计。我们确认通过描述并不在其分析中需要复杂的（组成），推理和可以简单的设计条件下安全地被屏蔽的FPGA实现的这些属性，被评价直接扩展到股票任意数量。我们提供了一个全面的性能和（最坏情况），我们设计的安全性分析，并与一个AES实现与面向领域的掩蔽方案保护的所获得的结果进行比较。结果表明，简单具有成本，这随着安全要求的提高少望而却步。

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