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首页> 外文期刊>Journal of electrical and computer engineering >Applying Partial Power-Gating to Direction-Sliced Network-on-Chip
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Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

机译：将部分电源门控应用于方向切片片上网络

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摘要

Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down; on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique; power-gating can be utilized in on-chip network to solve the crisis. However; the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper; we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme; an improved routing algorithm; and a deadlock recovery mechanism. In the synthetic traffic simulation; the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation; the design in the mesh/torus network consumes 15.2%/18.9% more power on average; whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance; the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.
机译：片上网络（NoC）是未来多核系统的关键通信体系结构之一。随着技术的不断缩小，片上网络解决了日益严重的泄漏功率危机。作为泄漏功率缓解技术；功率门控可用于片上网络以解决危机。然而;常规电源门控NoC的断开会严重影响网络性能。本文我们提出了一种新颖的部分功率门控方法，以改善功率门控NoC的性能。该方法主要涉及方向切片方案。改进的路由算法；以及死锁恢复机制。在综合交通仿真中；所提出的设计在低负载范围内显示出良好的电源效率，并且比传统的电源门控系统具有更好的性能。用于应用程序跟踪仿真；网状/环形网络中的设计平均多消耗15.2％/ 18.9％的功耗；与传统的电源门控设计相比，平均性能提高了45.0％/ 28.7％。总的来说;提出的具有部分功率门控的设计在性能和功率效率之间具有更好的权衡。

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  • 来源
    《Journal of electrical and computer engineering》 |2015年第2015期|862387.1-862387.16|共16页
  • 作者

    Feng Wang; Xiantuo Tang; Zuocheng Xing;

  • 作者单位

    National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, China;

    National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, China;

    National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, China;

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