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首页> 外文期刊>Journal of electrical and computer engineering >A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications
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A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

机译：使用双电荷泵控制技术的3.9μs稳定时间小数扩频时钟发生器，用于串行ATA应用

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摘要

A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 μs to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 μm CMOS and achieves settling time of 3.91 μs faster than 8.11 μs of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from -5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 μm and 18 mW, respectively.
机译：利用串行快速技术附件（SATA）应用开发了一种利用快速沉降双电荷泵（CP）技术的低抖动分数扩频时钟发生器（SSCG）。双CP架构通过缩小环路滤波器的有效电容将设计面积减小到60％。此外，建立时间减少了4μs，以便在建立时间的初始阶段仅通过main-CP向电容器充电。 SSCG采用0.13μmCMOS制成，建立时间比传统SSCG的8.11μs快3.91μs。 1.5 GHz的250个周期的随机抖动和总抖动分别小于3.2和10.7 psrms。三角调制信号频率为31.5 kHz，在1.5 GHz时调制偏差为-5000 ppm至0 ppm。 EMI降低10.0 dB。设计面积和功耗分别为300×700μm和18 mW。

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