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Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model

机译:混合模型:高效的对称多处理器参考模型

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摘要

Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems, particularly for symmetric multiprocessors. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources, and total personnel. Simulation-based verification is a long-standing approach used to locate design errors in the symmetric multiprocessor verification. The greatest challenge of simulation-based verification is the creation of the reference model of the symmetric multiprocessor. In this paper, we propose an efficient symmetric multiprocessor reference model, Hybrid Model, written with SystemC. SystemC can provide a high-level simulation environment and is faster than the traditional hardware description languages. Hybrid Model has been implemented in an efficient 32-bit symmetric multiprocessor verification. Experimental results show our proposed model is a fast, accurate, and efficient symmetric multiprocessor reference model and it is able to help designers to locate design errors easily and accurately.
机译:功能验证已成为嵌入式系统具有成本效益的设计中的主要瓶颈之一,特别是对于对称多处理器而言。据估计,整个验证最多占设计资源的60%,其中包括工期,计算机资源和总人员。基于仿真的验证是一种用于在对称多处理器验证中定位设计错误的长期方法。基于仿真的验证的最大挑战是对称多处理器参考模型的创建。在本文中,我们提出了一个有效的对称多处理器参考模型,即用SystemC编写的混合模型。 SystemC可以提供高级仿真环境,并且比传统的硬件描述语言要快。混合模型已在高效的32位对称多处理器验证中实现。实验结果表明,我们提出的模型是一种快速,准确,高效的对称多处理器参考模型,能够帮助设计人员轻松,准确地定位设计错误。

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  • 来源
    《Journal of electrical and computer engineering》 |2015年第2015期|915409.1-915409.10|共10页
  • 作者单位

    Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China;

    Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China;

    Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China;

    Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China;

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