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A System-layer Infrastructure for SoC Diagnosis

机译：SoC诊断的系统层基础架构

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摘要

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.
机译：在IC制造阶段，仅区分好芯片和故障芯片是不够的。实际上，特别是在新设备生产的第一阶段，迅速需要对可能出现的故障进行全面了解，以提高产量。对于测试工程师而言，处理片上系统（SoC）的制造测试意味着解决从有故障的芯片中提取诊断数据的问题。在产品生命周期的后续步骤中，诊断的另一个同等重要的目的是找到导致现场退货的硅不良行为的真正根本原因。在核心测试层，几乎必须采用面向诊断的可测试性设计结构，并且已经针对多种类型的核心制定了许多解决方案。诊断数据检索通常包括执行一组自测程序，其应用顺序和/或定制可能取决于获得的结果本身。本文详细介绍了能够有效管理SoC自诊断程序的系统层测试体系结构的特征。该架构由面向诊断的测试访问机制（TAM）和拥有足够智能以自动管理核心诊断程序的Infrastructure-IP组成。两者均设计为符合IEEE 1500标准的嵌入式核心测试标准，并利用插入的自测结构的特性来诊断内存，处理器和逻辑核心。这种用于SoC诊断的方法最大程度地减少了用于模式存储的ATE内存需求，并大大加快了诊断过程的完整执行速度。实验结果突出了该方法相对于可选的ATE驱动的诊断程序的便利性，同时诉诸于可忽略的区域开销。

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