Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

Hafizur Rahaman; Debesh K. Das; Bhargab B. Bhattacharya

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Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

机译：使用分层模块实现对称功能，以实现卡入和路径延迟故障可测试性

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摘要

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design, and uses only 2-input AND-OR gates. A universal test set of size (n 2/8 + 3n/4) for detecting all single stuck-at faults can be easily determined for an n-input module, where n = 2 k , k ≥ 3. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees full robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those of earlier designs. Results on circuit area and delay for a few benchmark examples are also reported.

机译：提出了一种使用分层模块实现完全对称布尔函数的技术。首先，设计一个简单的蜂窝模块来合成统一对称函数。该结构具有通用性，允许递归设计，并且仅使用2输入与或门。对于n输入模块，可以轻松确定用于检测所有单个卡住故障的通用测试集（n 2 / 8 + 3n / 4），其中n = 2 k ，k ≥3。然后按照统一分解方法实现一般的对称函数。综合程序保证了电路中完全鲁棒的路径延迟故障可测试性。在几个对称函数上的实验结果表明，与早期设计相比，所提出设计的硬件成本低，并且电路中的路径数量大大减少。还报告了一些基准示例的电路面积和延迟结果。

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来源
《Journal of Electronic Testing》 |2006年第2期|125-142|共18页
作者
Hafizur Rahaman; Debesh K. Das; Bhargab B. Bhattacharya;
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作者单位

Information Technology Department Bengal Engineering and Science University;

Computer Science Engineering Department Jadavpur University;

ACM Unit Indian Statistical Institute;

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原文格式 PDF
正文语种 eng
中图分类
关键词
path-delay fault; stuck-at fault; symmetric boolean function; synthesis-for-testability; unate function; universal tests;

机译：路径延迟故障;卡滞故障;对称布尔函数;可测性综合;统一函数;通用测试;

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专利

1. Implementing Symmetric Functions with Hierarchical Modules for Stuck-at and Path-Delay Fault Testability [J] . HAFIZUR RAHAMAN, DEBESH K. DAS, BHARGAB B. BHATTACHARYA Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2006,第2期

机译：使用分层模块实现对称功能以实现卡滞和路径延迟故障可测试性
2. A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults [J] . Subhashis Majumder, Bhargab B.Bhattacharya, Vishwani D.Agrawal, 计算机科学技术学报（英文版） . 2004,第006期

机译：滞留故障对路径延迟故障可测性的新分类
3. Synthesis of symmetric functions for path-delay fault testability [J] . Chakrabarti S., Das S. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2000,第9期

机译：路径延迟故障可测试性的对称函数的综合
4. Mapping symmetric functions to hierarchical modules for path-delay fault testability [C] . Rahaman H., Das D.K., Bhattacharya B.B. Test Symposium, 2003. ATS 2003. 12th Asian . 2003

机译：将对称函数映射到分层模块以实现路径延迟故障可测试性
5. A design for testability scheme for modular and non-modular Quantum Dot Cellular Automata (QCA) employing stuck-at fault model. [D] . Sultana, Sayeeda. 2006

机译：一种采用卡死模型的模块化和非模块化量子点元胞自动机（QCA）的可测试性方案设计。
6. Identification of functional hubs and modules by converting interactome networks into hierarchical ordering of proteins [O] . Young-Rae Cho, Aidong Zhang 2010

机译：通过将相互作用基因组网络转换为蛋白质的层次顺序来识别功能中心和模块
7. BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability [O] . Junhao Shi, Görschwin Fey, Rolf Drechsler 2008

机译：基于BDD的全路径延迟故障可测性对称函数综合
8. Requirements for implementing real-time control functional modules on a hierarchical parallel pipelined system [R] . Wheatley, Thomas E., Michaloski, John L., Lumia, Ronald 1989

机译：在分层并行流水线系统上实现实时控制功能模块的要求

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

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