...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Journal of Real-Time Image Processing >Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling
【24h】

Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling

机译：使用参数压缩背景建模的用于噪声自适应视频对象检测的嵌入式体系结构

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Video processing algorithms are computationally intensive and place stringent requirements on performance and efficiency of memory bandwidth and capacity. As such, efficient hardware accelerations are inevitable for fast video processing systems. In this paper, we propose resource- and power-optimized FPGA-based configurable architecture for video object detection by integrating noise estimation, Mixture-of-Gaussian background modeling, motion detection, and thresholding. Due to large amount of background modeling parameters, we propose a novel Gaussian parameter compression technique suitable for resource- and power-constraint embedded video systems. The proposed architecture is simulated, synthesized and verified for its functionality, accuracy and performance on a Virtex-5 FPGA-based embedded platform by directly interfacing to a digital video input. Intentional exploitation of heterogeneous resources in FPGAs, and advanced design techniques such as heavy pipelining and data parallelism yield real-time processing of HD-1080p video streams at 30 frames per second. Objective and subjective evaluations to existing hardware-based methods show that the proposed architecture obtains orders of magnitude performance improvements, while utilizing minimal hardware resources. This work is an early attempt to devise a complete video surveillance system onto a stand-alone resource-constraint FPGA-based smart camera.
机译：视频处理算法的计算量很大，并且对存储带宽和容量的性能和效率提出了严格的要求。这样，对于快速视频处理系统来说，有效的硬件加速是不可避免的。在本文中，我们通过集成噪声估计，高斯混合背景建模，运动检测和阈值，为视频对象检测提出了一种基于资源和功耗优化的基于FPGA的可配置体系结构。由于大量的背景建模参数，我们提出了一种适用于资源和功率受限的嵌入式视频系统的新型高斯参数压缩技术。通过直接与数字视频输入接口，可以在基于Virtex-5 FPGA的嵌入式平台上对所提出的体系结构的功能，准确性和性能进行仿真，综合和验证。对FPGA中异构资源的有意开发以及繁重的流水线处理和数据并行化等先进的设计技术可以以每秒30帧的速度实时处理HD-1080p视频流。对现有的基于硬件的方法进行客观和主观评估表明，所建议的体系结构在使用最少硬件资源的同时，获得了数量级的性能改进。这项工作是将完整的视频监视系统设计到基于FPGA的独立资源受限智能相机的早期尝试。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号