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FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration

机译：基于FPGA的IP核实现，用于使用动态部分重配置进行人脸识别

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摘要

This paper presents a combination of novel feature vectors construction approach for face recognition using discrete wavelet transform (DWT) and field programmable gate array (FPGA)-based intellectual property (IP) core implementation of transform block in face recognition systems. Initially, four experiments have been conducted including the DWT feature selection and filter choice, features optimisation by coefficient selections and feature threshold. To examine the most suitable method of feature extraction, different wavelet quadrant and scales have been evaluated, and it is followed with an evaluation of different wavelet filter choices and their impact on recognition accuracy. In this study, an approach for face recognition based on coefficient selection for DWT is presented, and the significant of DWT coefficient threshold selection is also analysed. For the hardware implementation, two architectures for two-dimensional (2-D) Haar wavelet transform (HWT) IP core with transpose-based computation and dynamic partial reconfiguration (DPR) have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are also discussed in this paper.
机译：本文提出了一种新颖的特征向量构造方法，该方法利用离散小波变换（DWT）和基于现场可编程门阵列（FPGA）的知识产权（IP）核心的人脸识别系统实现了人脸识别。最初，已进行了四个实验，包括DWT特征选择和滤波器选择，通过系数选择和特征阈值进行特征优化。为了检查最合适的特征提取方法，对不同的小波象限和尺度进行了评估，然后评估了不同的小波滤波器选择及其对识别精度的影响。该研究提出了一种基于系数选择的DWT人脸识别方法，并分析了DWT系数阈值选择的意义。对于硬件实现，已经使用VHDL合成了具有基于转置的计算和动态部分重配置（DPR）的二维（2-D）Haar小波变换（HWT）IP内核的两种架构，并已在Xilinx Virtex-5 FPGA上实现。本文还讨论了使用部分和非部分重新配置过程进行的不同配置之间的实验结果和比较，以及对面积，功耗和最大频率的详细性能分析。

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  • 来源
    《Journal of Real-Time Image Processing》 |2013年第3期|327-340|共14页
  • 作者

    Afandi Ahmad; Abbes Amira; Paul Nicholl; Benjamin Krill;

  • 作者单位

    Department of Computer Engineering, Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia (UTHM), Johor, Malaysia;

    Nanotechnology and Integrated Bio-Engineering Centre (NIBEC), Faculty of Computing and Engineering, University of Ulster (Jordanstown Campus), Ulster, Northern Ireland Department of Electrical Engineering, College of Engineering, Qatar University, Doha, Qatar;

    School of Electronic, Electrical Engineering and Computer Science, The Queens University, Belfast, Northern Ireland;

    Nanotechnology and Integrated Bio-Engineering Centre (NIBEC), Faculty of Computing and Engineering, University of Ulster (Jordanstown Campus), Ulster, Northern Ireland;

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  • 正文语种 eng
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  • 关键词

    Field programmable gate array (FPGA); Face recognition; Discrete wavelet transform (DWT); Dynamic partial reconfiguration (DPR);

    机译：现场可编程门阵列（FPGA）;人脸识别;离散小波变换（DWT）;动态部分重配置（DPR）;

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