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首页> 外文期刊>Journal of Real-Time Image Processing >Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications
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Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

机译：由FPGA动态部分自重配置支持的实时嵌入式系统：针对生物识别应用的案例研究

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This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by hardware/software (HW/SW) co-design and run-time reconfigurable computing, is synthesizable in SRAM-based programmable logic. As proof-of-concept, a run-time partially reconfigurable field-programmable gate array (FPGA) is addressed to carry out a specific application of high-demanding computational power such as an automatic fingerprint authentication system (AFAS). Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order. In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region of the FPGA. The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical algorithm partitioned in HW/SW tasks operating at 50 or 100 MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative. These results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost. Such features, reached through partial reconfiguration, are easily portable today to a broad range of embedded applications with identical system architecture.
机译：这项工作旨在为应用于嵌入式电子应用程序的高效开放系统架构铺平道路，以实时，低成本地管理复杂计算算法的处理。目标是定义一种标准架构，该架构能够增强当今市场上其他替代产品（如通用多核处理器）提供的性能-成本之间的权衡。我们的方法由硬件/软件（HW / SW）协同设计和运行时可重配置计算支持，可在基于SRAM的可编程逻辑中进行综合。作为概念验证，解决了运行时部分可重新配置的现场可编程门阵列（FPGA），以执行高要求的计算能力的特定应用，例如自动指纹认证系统（AFAS）。生物识别个人识别是计算密集型算法的一个很好的示例，该算法由一系列按顺序执行的图像处理任务组成。在我们的先驱构想中，首先在一系列协处理器中对这些任务进行分区和综合，然后在FPGA的部分可重新配置区域上对这些任务进行实例化并在时间上对其进行多路复用。 AFAS的实现基准是在PC平台上双核处理器（1.83 GHz的Intel Core 2 Duo T5600）下的纯软件方法，还是可重新配置的FPGA协同设计（在硬件/软件任务运行中划分的相同算法）在Xilinx Virtex-4 LX系列第二小的器件上以50或100 MHz的频率工作时）突出显示了一个数量级的加速，从而支持FPGA替代方案。这些结果表明，生物特征识别是运行时可重配置计算的明智杀手级应用，主要是在有效平衡计算能力，功能灵活性和成本方面。通过部分重新配置实现的这些功能如今可以轻松地移植到具有相同系统架构的各种嵌入式应用程序中。

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