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首页> 外文期刊>Journal of Scientific & Industrial Research >Comparison of pipelined IEEE-754 standard floating point adder with unpipelined adder
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Comparison of pipelined IEEE-754 standard floating point adder with unpipelined adder

机译：流水线IEEE-754标准浮点加法器与非流水线加法器的比较

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摘要

Many Digital Signal Processing (DSP) algorithms use floating-point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal of every VLSI designer. This paper presents a comparison of pipelined floating-point adder complaint with IEEE 754 format with an unpipelined adder also complaint with IEEE 754 format. It describes the IEEE floating-point standard 754. A pipelined floating point adder based on IEEE 754 format, is developed and the design is compared with that of an unpipelined floating point adder and a rigorous analysis is done for speed, area, and power considerations. The functional partitioning of the adder into four distinct stages operates simultaneously for different serial input data stream. It not only increases the speed but also is energy efficient. All these improvements are at the cost of slight increase in the chip area. The basic methodology, and approach used for VHDL (Very Large Scale Integration Hardware Descriptive Language) implementation of the floating-point adder are also described. Detailed synthesis report operated upon Xilinx ISE 5.2i software and Modelsim is given. The hardware design is implemented on Spartan IIE FPGA chip.
机译：许多数字信号处理（DSP）算法使用浮点算法，这需要每秒执行数百万次计算。对于这种严格的要求，快速，精确和高效的电路设计是每个VLSI设计人员的目标。本文对IEEE 754格式的流水线浮点加法器投诉与IEEE 754格式的非流水线加法器投诉进行了比较。它描述了IEEE浮点标准754。开发了一个基于IEEE 754格式的流水线浮点加法器，并将其设计与非流水线浮点加法器进行了比较，并对速度，面积和功耗进行了严格的分析。 。加法器的功能划分为四个不同的阶段，同时针对不同的串行输入数据流进行操作。它不仅可以提高速度，而且还具有能源效率。所有这些改进都以芯片面积略有增加为代价。还介绍了用于浮点加法器的VHDL（超大规模集成硬件描述语言）实现的基本方法和方法。给出了在Xilinx ISE 5.2i软件和Modelsim上运行的详细综合报告。硬件设计在Spartan IIE FPGA芯片上实现。

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